LM2657
Dual Synchronous Buck Regulator Controller
General Description
The LM2657 is an adjustable 200kHz-500kHz dual channel
voltage-mode controlled high-speed synchronous buck
regulator controller ideally suited for high current applica-
tions. The LM2657 requires only N-channel FETs for both
the upper and lower positions of each stage. It features line
feedforward to improve the response to input transients. At
very light loads, the user can choose between the high-
efficiency Pulse-skip mode or the constant frequency
Forced-PWM mode. Lossless current limiting without the use
of external sense resistors is made possible by sensing the
voltage drop across the bottom FET. A unique adaptive duty
cycle clamping technique is incorporated to significantly re-
duce peak currents under abnormal load conditions. The two
independently programmable outputs switch 180 out of
phase (interleaved switching) reducing the input capacitor
and filter requirements. The input voltage range is 4.5V to
28V while the output voltages are adjustable down to 0.6V.
Standard supervisory and control features include Soft-start,
Power Good, output Under-voltage and Over-voltage protec-
tion, Under-voltage Lockout, and chip Enable.
Features
n
Input voltage range from 4.5V to 28V
n
Synchronous dual-channel interleaved switching
n
Forced-PWM or Pulse-skip modes
n
Lossless bottom-side FET current sensing
n
Adaptive duty cycle clamp
n
High current N-channel FET drivers
n
Low shutdown supply current
n
Reference voltage accurate to within
1.5%
n
Output voltage adjustable down to 0.6V
n
Power Good flag and Chip Enable
n
Under-voltage lockout
n
Over-voltage/Under-voltage protection
n
Soft-start
n
Switching frequency adjustable 200kHz-500kHz
n
TSSOP-28 package
Applications
n
Low Output Voltage High-Efficiency Buck Regulators
Typical Application (Channel 2 in parenthesis)
20134704
January 2005
LM2657
Dual
Synchronous
Buck
Regulator
Controller
2005 National Semiconductor Corporation
DS201347
www.national.com
Typical Application (Channel 2 in parenthesis)
(Continued)
Connection Diagram
20134702
Top View
Ordering Information
Order Number
Package Drawing
Supplied As
LM2657MTC
MTC28
48 Units/Rail
LM2657MTCX
MTC28
2500 Units/13" Reel
Pin Description
Pin 1, SENSE1: Output voltage sense pin for Channel 1. It is
tied directly to the output rail. The SENSE pin voltage is used
by the IC, together with the VIN voltage (Pin 22) to calculate
the CCM (continuous conduction mode) duty cycle. This is
used by the IC to set the minimum duty cycle in the SKIP
mode to 85% of the CCM value. It is also used to set the
adaptive duty cycle clamp (see Pin 3).
Pin 2, FB1: Feedback pin for Channel 1. This is the inverting
input of the channel's error amplifier. The voltage on this pin
under regulation is nominally at 0.6V. A `Power Good win-
dow' on this pin determines if the output voltage is within
regulation limits (
13%). If the voltage (on either channel)
falls outside this window for more than 7s, `Power Not
Good' is signaled on the PGOOD pin (Pin 9). Additionally, if
the FB voltage is above the upper limit, an over-voltage fault
condition occurs which turns on the low-side FET. The part
will resume normal operation on the next high side cycle in
which no fault is detected. When single channel operation is
desired (one channel is used, the other is disabled), the
feedback pins of both channels must be connected together,
near the IC. All other pins specific to the unused channel
should be left floating (not connected to each other, either).
Pin 3, COMP1: Compensation pin for Channel 1. This is the
output of the error amplifier. The voltage level on this pin is
compared with an internally generated ramp signal to set the
duty cycle for normal regulation. Since the Feedback pin is
the inverting input of the same error amplifier, the appropri-
ate control loop compensation components are placed be-
tween this pin and the Feedback pin. The COMP pin is
internally pulled low during Soft-start to limit the duty cycle.
Once Soft-start is completed, the voltage on this pin can take
up the value required to maintain output regulation. Note that
an internal voltage clamp does not allow the pin to go much
higher than the steady-state requirement. This forms the
`adaptive duty cycle clamp' circuit, which serves to limit the
maximum allowable duty cycle and peak currents under
sudden overloads. Also note that this clamp has been de-
signed with enough `headroom' to permit an adequate re-
sponse to step loads within normal operating range.
Pin 4, SS1: Channel 1 Soft-start pin. A Soft-start capacitor is
placed between this pin and ground. A typical capacitance of
0.1F is recommended. During startup using chip Enable/
power-up, soft-start is reset by connecting an internal 1.8 k
resistor between this pin and ground (R
SS_DCHG
, see Elec-
trical Characteristics table). It discharges any remaining
charge on the Soft-start capacitors to ensure that the voltage
on both Soft-start pins is below 100mV. Reset having thus
been obtained, an 11A current source at this pin charges up
the Soft-start capacitor. The voltage on this pin controls the
maximum duty cycle, and this produces a gradual ramp-up
of the output voltage, thereby preventing large inrush cur-
rents into the output capacitors. The voltage on this pin
finally clamps close to 5V. During current limit, V
DD
UVLO, or
V
IN
UVLO this pin is connected to an internal 115A current
sink whenever a current limit event is in progress. This sink
current quickly discharges the Soft-start capacitor and forces
the duty cycle low to protect the power components.
Pin 5, VDD: 5V supply rail for the control and logic sections
of both channels. For normal operation to start, the voltage
on this pin must be brought above 4.5V. Subsequently, the
voltage on this pin (including any ripple component) should
not be allowed to fall below 4V for a duration longer than 7s.
Since this pin is also the supply rail for the internal control
sections, it should be well-decoupled particularly at high
frequencies. A minimum 0.1F-0.47F (ceramic) capacitor
should be placed on the component side very close to the IC
LM2657
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2
Pin Description
(Continued)
with no intervening vias between this capacitor and the
V
DD
/SGND pins. If the voltage on Pin 5 falls below the lower
UVLO threshold, the upper and lower FETs are both turned
OFF. `Power Not Good' is also signaled immediately (on Pin
9.) Normal operation will resume once the fault condition has
cleared. Additionally if the voltage on this pin falls below the
minimum voltage required for logic operation (about 1.8V
typ) the part will shutdown identically to enable (see pin 8)
being pulled low.
Pin 6, FREQ: Frequency adjust pin. The switching frequency
(for both channels) is set by a resistor connected between
this pin and ground. A value of 22.1k
sets the frequency to
300kHz (nominal). If the resistance is increased, the switch-
ing frequency falls. An approximate relationship is that for
every 7.3k
increase (or decrease) in the value of the fre-
quency adjust resistance, the time period (1/f) increases (or
decreases) by about 1s.
Pin 7, SGND: Signal Ground pin. This is the lower rail for the
control and logic sections of both channels. SGND should be
connected on the PCB to the system ground, which in turn is
connected to PGND1 and PGND2. The layout is important
and the recommendations in the section Layout Guidelines
should be followed.
Pin 8, EN: IC Enable pin. When EN is taken high, both
channels are enabled by means of a Soft-start power-up
sequence (see Pin 4). When EN is brought low, `Power Not
Good' is signaled within 100ns. The Soft-start capacitor is
then discharged by an internal 1.8k
resistor (R
SS_DCHG
,
see Electrical Characteristics table) to ground.
Pin 9, PGOOD: Power Good output pin. An open-Drain logic
output that is pulled high with an external pull-up resistor,
indicating that both output voltages are within a pre-defined
`Power Good' window, V
IN
and V
DD
are within required op-
erating range, and enable is high. Outside this window, this
pin is internally pulled low (`Power Not Good' signaled) pro-
vided the output error lasts for more than 7s. The pin also
goes low within 100ns of the Enable pin being taken low, or
V
DD
going below UVLO, or V
IN
going below UVLO irrespec-
tive of the output voltage level. Regulation on both channels
must be achieved first before fault monitoring becomes ac-
tive (i.e. PGOOD must have been high prior to occurrence of
the fault condition for a fault to be asserted). For correct
signaling on this pin under single-channel operation, see
description of Pin 2.
Pin 10, FPWM: Logic input for selecting either the Forced
PWM (`FPWM') Mode or Pulse-skip Mode (`SKIP') for both
channels (together). When the pin is driven high, the IC
operates in the FPWM mode, and when pulled low or left
floating, the SKIP mode is enabled. In FPWM mode, the
lower FET of a given channel is always ON whenever the
upper FET is OFF (except for a narrow shoot-through pro-
tection deadband). This leads to continuous conduction
mode of operation, which has a fixed frequency and (almost)
fixed duty cycle down to very light loads. But this does
reduce efficiency at light loads. The alternative is the SKIP
mode, where the lower FET remains ON only till the voltage
on the Switch pin (see Pin 27 or Pin 16) goes above -2.2mV
(typical). So for example, for a 21m
FET, this translates to
a current threshold of 2.2/21 = 0.1A. Therefore if the (instan-
taneous) inductor current falls below this value, the lower
FET will turn OFF every cycle at this point (when operated in
SKIP mode). This threshold is set by the `Zero-cross Com-
parator' in the Block Diagram. Note that if the inductor cur-
rent waveform is high enough to cause the SW pin to be
always below this `zero-cross threshold' (see Electrical Char-
acteristics table), there will be no observable difference be-
tween FPWM and SKIP mode settings (in steady-state).
SKIP mode, when it occurs, is clearly a discontinuous mode
of operation. However, in conventional discontinuous mode,
the duty cycle keeps falling (towards zero) as the load de-
creases. But the LM2657 does not `allow' the duty cycle to
fall by more than 15% of its original value (at the CCM-DCM
boundary). This leads to pulse-skipping, and so the average
frequency decreases as the load decreases. This mode of
operation improves efficiency at light loads, but the fre-
quency is effectively no longer a constant. Note that a mini-
mum preload of 0.1mA should be maintained on the output
of each channel to ensure regulation in SKIP mode. The
resistive divider from output to ground used to set the output
voltage could be designed to serve as this preload.
Pin 11, SS2: Soft-start pin for Channel 2. See Pin 4.
Pin 12, COMP2: Compensation pin for Channel 2. See Pin
3.
Pin 13, FB2: Feedback pin for Channel 2. See Pin 2.
Pin 14, SENSE2: Output voltage sense pin for Channel 2.
See Pin 1.
Pin 15, ILIM2: Channel 2 Current Limit pin. When the bottom
FET is ON, a 62A (typical) current flows out of this pin into
an external current limit setting resistor connected to the
drain of the lower FET. This is a current source so the drop
across this resistor tries to push the voltage on this pin to a
more positive value. However, the drain of the lower FET,
which is connected to the other side of the same resistor, is
trying to go more negative as the load current increases.
Therefore at some value of current, the voltage on this pin
will cross zero and start to go negative. This is the current
limiting condition and it is detected by the `Current Limit
Comparator' seen in the Block Diagram. When a current limit
condition has been detected, the next ON-pulse of the upper
FET will be omitted. The lower FET will again be monitored
to determine if the current has fallen below the threshold. If it
has, the next ON-pulse will be permitted. If not, the upper
FET will stay OFF, and remain so for several cycles if nec-
essary, until the current returns to normal. Eventually, if the
overcurrent condition persists and the upper FET has not
been turned ON, the output will start to fall eventually trig-
gering "Power not Good".
Pin 16, SW2: The Switching node of the buck regulator of
Channel 2. Also serves as the lower rail of the floating driver
of the upper FET.
Pin 17, HDRV2: Gate drive pin for the upper FET of Channel
2 (High-side drive). The top gate driver is interlocked with the
bottom
gate
driver
to
prevent
shoot-through/cross-
conduction.
Pin 18, BOOT2: Bootstrap pin for Channel 2. This is the
upper supply rail for the floating driver of the upper FET. It is
bootstrapped by means of a ceramic capacitor connected to
the channel Switching node. This capacitor is charged up by
the IC to a value of about 5V as derived from the V5 pin (Pin
21).
Pin 19, PGND2: Power Ground pin of Channel 2. This is the
return path for the bottom FET gate drive. Both the PGND's
are to be connected on the PCB to the system ground and
also to the Signal ground (Pin 7) in accordance with the
recommended Layout Guidelines .
Pin 20, LDRV2: Gate drive pin for the Channel 2 bottom FET
(Low-side drive). The bottom gate driver is interlocked with
the
top
gate
driver
to
prevent
shoot-through/cross-
conduction.
LM2657
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3
Pin Description
(Continued)
Pin 21, V5: Upper rail of the lower FET drivers of both
channels. Also used to charge up the bootstrap capacitors of
the upper FET drivers. This is connected to an external 5V
supply. The 5V rail may be the same as the rail used to
provide power to the VDD pin (Pin 5). If these rails are
connected, the VDD pin must be well-decoupled so that it
does not interact with the V5 pin. A minimum 0.1F (ceramic)
capacitor should be placed on the component side very
close to the IC with no intervening vias between this capaci-
tor and the V5/PGND pins.
Pin 22, VIN: The input that powers both the buck regulator
channels. It also is used by the internal ramp generator to
implement the line `feedforward' feature. The VIN pin is also
used with the SENSE pin voltage to predict the CCM (con-
tinuous conduction mode) duty cycle and to thereby set the
minimum allowed DCM duty cycle to 85% of the CCM value
(in SKIP mode, see Pin 10). This is a high input impedance
pin, drawing only about 115A from the input rail. A fault
condition will occur if this voltage drops below its UVLO
threshold.
Pin 23, LDRV1: LDRV pin of Channel 1. See Pin 20.
Pin 24, PGND1: PGND pin for Channel 1.See Pin 19.
Pin 25, BOOT1: Boot pin of Channel 1. See Pin 18.
Pin 26, HDRV1: HDRV pin of Channel 1. See Pin 17.
Pin 27, SW1: SW pin of Channel 1. See Pin 16.
Pin 28, ILIM1: Channel 1 Current Limit pin. See Pin 15.
LM2657
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4
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltages from the indicated pins to GND unless otherwise
indicated (Note 2):
VIN
-0.3V to 30V
V5
-0.3V to 7V
VDD
-0.3V to 7V
BOOT1, BOOT2
-0.3V to 36V
BOOT1 to SW1, BOOT2 to
SW2
-0.3V to 7V
SW1, SW2
-0.3V to 30V
ILIM1, ILIM2
-0.3V to 30V
SENSE1, SENSE2, FB1, FB2
-0.3V to 7V
PGOOD
-0.3V to 7V
EN
-0.3V to 7V
Junction Temperature
+150C
ESD Rating (Note 3)
2kV
Ambient Storage Temperature
Range
-65C to +150C
Soldering Dwell Time,
Temperature
Wave
Infrared
Vapor Phase
4 sec, 260C
10 sec, 240C
75 sec, 219C
Operating Ratings
(Note 1)
VIN
4.5V to 28V
VDD, V5
4.5V to 5.5V
Junction Temperature
-40C to +125C
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25C, and those with boldface apply over full
Operating Junction Temperature range. VDD = V5 = 5V, V
SGND
= V
PGND
= 0V, VIN = 15V, V
EN
= 3V, R
FADJ
= 22.1k
un-
less otherwise stated (Note 4). Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Min
Typical
(Note
5)
Max
Units
Reference
V
FB
FB Pin Voltage at
Regualtion (either FB Pin)
VDD = 4.5V to 5.5V,
VIN = 4.5V to 28V
591
600
609
mV
V
FB_LINE REG
V
FB
Line Regulation (
V
FB
)
VDD = 4.5V to 5.5V,
VIN = 4.5V to 28V
0.5
I
FB
FB Pin Current (sourcing)
V
FB
at regulation
20
100
nA
Chip Supply
I
Q_VIN
VIN Quiescent Current
V
FB1
= V
FB2
= 0.7V
100
200
A
I
SD_VIN
VIN Shutdown Current
V
EN
= 0V
0
5
A
I
Q_VDD
VDD Quiescent Current
V
FB1
= V
FB2
= 0.7V
2.5
4
mA
I
SD_VDD
VDD Shutdown Current
V
EN
= 0V
6
15
A
I
Q_V5
V5 Normal Operating
Current
V
FB1
= V
FB2
= 0.7V
0.3
0.5
mA
V
FB1
= V
FB2
= 0.5V
1
1.5
I
SD_V5
V5 Shutdown Current
V
EN
= 0V
0
5
A
I
Q_BOOT
BOOT Quiescent Current
V
FB1
= V
FB2
= 0.7V
2
5
A
V
FB1
= V
FB2
= 0.5V
300
500
I
SD_BOOT
BOOT Shutdown Current
V
EN
= 0V
1
5
A
V
DD_UVLO
VDD UVLO Threshold
VDD rising up to V
UVLO
3.9
4.2
4.5
V
VDD UVLO Hysteresis
VDD = V5 falling from V
UVLO
0.5
0.7
0.9
V
V
IN_UVLO
VIN UVLO Threshold
VIN rising up to V
UVLO
3.9
4.2
4.5
V
VIN UVLO Hysteresis
VIN falling from V
UVLO
0.1
0.3
V
Logic
I
EN
EN Input Current
V
EN
= 0 to 5V
0
A
V
EN_HI
Minimum EN Input Logic
High
2
V
V
EN_LO
Maximum EN Input Logic
Low
0.8
V
R
FPWM
FPWM Pull-down
V
FPWM
= 2V
100
200
1000
k
LM2657
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5
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