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This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000121-01, First Edition, June 2000.
This document describes revision A of the LSI Logic Corporation L64777 DVB
QAM Modulator and will remain the official reference source for all revisions of
this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, G10, and the G10 logo design, are trademarks or
registered trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.
Preface
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Preface
This book is the primary reference and technical manual for the L64777
DVB QAM Modulator. It contains a complete functional description for the
L64777 and includes complete physical and electrical specifications for
the L64777.
Audience
This document assumes that you have some familiarity with digital video
broadcasting, QAM modulators, and related support devices. The people
who benefit from this book are:
Engineers and managers who are evaluating the modulator for
possible use in a system
Engineers who are designing the modulator into a system
Organization
This document has the following chapters and appendixes:
Chapter 1, Introduction
, introduces the L64777 DVB QAM
Modulator.
Chapter 2, Modulator Architecture
, describes the functional
components of the L64777.
Chapter 3, Interfaces
, describes the L64777 interfaces.
Chapter 4, Register Descriptions
, describes the registers used to
configure and monitor the L64777.
Chapter 5, Signals
, presents the signal definitions for the L64777.
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Preface
Chapter 6, Specifications
, presents the electrical and timing
specifications for the L64777. It also presents the pinout and
packaging information.
Appendix A, Programming the L64777 in Serial Host Interface
Mode
, discusses how to program the L64777 internal registers and
data tables in serial host interface mode.
Appendix B, PLL Divider Settings and L64724/34 Connection
,
lists the PLL divider settings for typical applications. It also describes
the L64777 connection to the L64724.
Appendix C, Monitoring Device Internal Signals
, describes how to
program test register (14) for monitoring of device internal signals.
Related Publications
Digital Broadcasting Systems for Television Sound and Data Services:
Framing Structure, Channel Coding and Modulation Cable Systems
ETS 300 429, September 1996.
Generic Coding of Moving Pictures and Associated Audio,
ISO/IEC 13818-1, MPEG2 Systems, November 1994.
G10
-p CW900100 10-Bit Direct Digital Synthesis Digital-to-Analog
Converter, Preliminary Datasheet, LSI Logic, September 1998.
L64724 Satellite Receiver Technical Manual, LSI Logic, April 2000, order
number I14030.
Conventions Used in This Manual
The word
assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.
Contents
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Contents
Chapter 1
Introduction
1.1
Overview
1-1
1.2
Operating Environment
1-2
Chapter 2
Modulator Architecture
2.1
Introduction
2-2
2.2
PLL Modes
2-4
2.2.1
PLL Mode 1
2-4
2.2.2
PLL Mode 2
2-5
2.3
I/O
2-6
2.3.1
Input
2-6
2.3.2
Output Signals
2-6
2.3.3
Control Interface
2-8
2.3.4
Serial Microprocessor Interface
2-10
2.4
Input Synchronization
2-10
2.4.1
Sync Acquisition Phase
2-13
2.4.2
Sync Tracking Phase
2-14
2.5
FIFO Clock Conversion
2-16
2.6
Sync/EF Reinsertion Unit
2-17
2.6.1
Sync Insertion Mode
2-18
2.6.2
Error Flag Insertion
2-18
2.6.3
Energy Dispersal (Scrambler) Unit
2-18
2.7
Reed-Solomon Encoder
2-20
2.7.1
Forward Error Correction (FEC)
2-21
2.7.2
Error Handling and Correction
2-22
2.8
Convolutional Interleaver
2-23
2.9
Bytes to M-tuples Converter
2-24
2.10
Differential Encoder and QAM Mapping
2-26
2.11
Square Root Nyquist Filter
2-27
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