DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Advance Information
LOGIC Devices Incorporated
1
Sept 30, 2002 LDS.3312 B
Video Imaging Product
Features in the Four Modes With
Asynchronous FIFOs:
Near-Full/Empty Flags With Programmable
Thresholds
Features in the Six Purely Sequential (FIFO,
shift register) Modes:
Up to 100 MHz Continuous Data
Throughput Rate
Features in the Two Random Access (non-
FIFO) Modes:
Up to 100 MHz Data Rate
LF3312s may be Connected in Parallel for
HDTV, Multiframe SDTV, etc.
Built-in ITUR-656 TRS detection and
Synchronization
User-Set/Resettable Read and Write Pointers
Choice of Control Interfaces:
Two-wire Serial Microprocessor Interface
Parallel Microprocessor Interface
Input Enable Control (Write Mask)
Output Enable Control (Data Skipping)
169 ball BGA
1.8V Internal Core Power Supply
3.3V I/O Supply
5V-Tolerant I/O
Field-Based or Frame-Based Comb Filtering
Image or Data Sequence Capture
Resynchronization of Data Streams
Video Special Effects (Rotation, Zoom, Picture-in-Picture)
Test Pattern Generation
High Speed Data Buffering
Motion Detection or Frame-to-Frame Correlation
Closed Circuit or Security Camera Systems
12,441,600-bit Frame Memory
May be Organized Into the Following
Configurations:
1,555,200 x 8-bit (single channel)
1,244,160 x 10-bit (single channel)
1,036,800 x 12-bit (single channel)
777,600 x 16-bit (single channel)
622,080 x 20-bit (single channel)
518,400 x 24-bit (single channel)
777,600 x 8-bit
(each of two parallel channels)
622,080 x 10-bit (each of two parallel channels)
518,400 x 12-bit (each of two parallel channels)
Eight Operating Modes:
One-Channel Synchronous Shift Register (Single
Clock Source)
One-Channel Framestore With Sequential Write
and Random Access Read
One-Channel Framestore With Random Access
Write and Sequential Read
One-Channel FIFO With Asynchronous I/O
Two-Channel Synchronous Shift Register (Single
Clock Source)
FIFO + shift register; Channel B Synchronized to
Channel A
Shift register + FIFO; Channel A Synchronized to
Channel B
Two-Channel FIFO; Both Channels Sychronized
to External Signal (a)
(a) power-up default mode
Features
Applications
DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Advance Information
LOGIC Devices Incorporated
2
Sept 30, 2002 LDS.3312 B
Video Imaging Product
The LF3312 is a 12,441,600-bit memory chip which can be configured by the user into either a two-data-
port single-channel or a four-data-port dual-channel architecture. The input data ports may be clocked
simultaneously or asynchronously with one another and with the output ports. Using the four 12-bit data
ports provided, the user can operate the chip as one or two 8-, 10-, or 12-bit channels or as a single 16-,
20-, or 24-bit channel, without wasting any memory resources. Since reads are non-destructive, a given
data value, once written into the memory core, may be read as many times as desired. A user requiring
more storage can cascade up to sixteen LF3312s into a larger array. The device is controlled by sixteen
instruction words of eight bits each, which may be programmed or verified via a standard I
2
C 2-wire serial
or parallel microprocessor interface.
The 3-bit OPMODE control selects one of the chip's eight distinct operating modes, each of which has
versatile submode options:
- One-Channel FIFO With Asynchronous I/O
- Two-Channel FIFO; Both Channels Sychronized to External Signal
- One-Channel Synchronous Shift Register (Single Clock; User-set Latency)
- Two-Channel Synchronous Shift Register (Single Clock; User-set Latencies)
- One-Channel Framestore With Sequential Write and Random Access Read
- One-Channel Framestore With Random Access Write and Sequential Read
- Two-Channel FIFO; Channel A Synchronized to Channel B
- Two-Channel FIFO; Channel B Synchronized to Channel A
LF3312 Overview
6-Mbit
MEMORY CELL
ARRAY
AIN
0
AIN
1
AIN
2
AIN
3
AIN
4
AIN
5
AIN
6
AIN
7
AIN
8
AIN
9
AIN
10
AIN
11
I
N
P
U
T
C
O
N
T
R
O
L
L
E
R
BIN
0*
BIN
1*
BIN
2*
BIN
3*
BIN
4*
BIN
5*
BIN
6*
BIN
7*
BIN
8*
BIN
9*
BIN
10*
BIN
11*
I
N
P
U
T
C
O
N
T
R
O
L
L
E
R
AOUT
0
AOUT
1
AOUT
2
AOUT
3
AOUT
4
AOUT
5
AOUT
6
AOUT
7
AOUT
8
AOUT
9
AOUT
10
AOUT
11
O
U
T
P
U
T
C
O
N
T
R
O
L
L
E
R
BOUT
0**
BOUT
1**
BOUT
2**
BOUT
3**
BOUT
4**
BOUT
5**
BOUT
6**
BOUT
7**
BOUT
8**
BOUT
9**
BOUT
10**
BOUT
11**
O
U
T
P
U
T
C
O
N
T
R
O
L
L
E
R
6-Mbit
MEMORY CELL
ARRAY
WRITE CONTROL
READ CONTROL
AIEN, BIEN
RCLK
* Doubles as lower portion of random address input
AOE
BOE
** Do bles as pper portion of random address inp t
AWEN, BWEN
ASET, BSET
ACLR, BCLR
AREN, BREN
RSET, RCLR
FLAG
GENERATOR
APF, APE
ACOLLIDE, BCOLLIDE
BPF, BPE
AMARK, BMARK
AWCLK, BWCLK
DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Advance Information
LOGIC Devices Incorporated
3
Sept 30, 2002 LDS.3312 B
Video Imaging Product
LF3312 Functional Block Diagram
PDF 
ZIP
