4-1
HIP9011
Engine Knock Signal Processor
The HIP9011 is used to provide a method of detecting
premature detonation often referred to as "Knock or Ping" in
internal combustion engines.
The IC is shown in the Simplified Block Diagram. The chip
can select between one of two sensors, if needed for
accurate monitoring or for "V" type engines. Internal control
via the SPI bus is fast enough to switch sensors between
each firing cycle. A programmable bandpass filter
processes the signal from either of the sensor inputs. The
bandpass filter can be selected to optimize the extraction
the engine knock or ping signals from the engine
background noise. Further single processing is obtained by
full wave rectification of the filtered signal and applying it to
an integrator whose output voltage level is proportional to
the knock signal amplitude. The chip is under
microprocessor control via a SPI interface bus.
Features
Two Sensor Inputs
Microprocessor Programmable
Accurate and Stable Filter Elements
Digitally Programmable Gain
Digitally Programmable Time Constants
Digitally Programmable Filter Characteristics
On-Chip Crystal Oscillator
Programmable Frequency Divider
External Clock Frequencies up to 24MHz
- 4, 5, 6, 8, 10, 12, 16, 20, and 24MHz
Operating Temperature Range -40
o
C to 125
o
C
Applications
Engine Knock Detector Processor
Analog Signal Processing Where Controllable Filter
Characteristics are Required
Simplified Block Diagram
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HIP9011AB
-40 to 125
20 Ld SOIC
M20.3
INTOUT
PROGRAMMABLE
2
-
0.111
RECTIFIER
PROGRAMMABLE
INTEGRATOR
40
-
600
s
32 STEPS
OUTPUT
DRIVER
ANTIALIASING FIL
TER
3RD ORDER
CHANNEL SELECT
SWITCHES
PROGRAMMABLE
BANDPASS
FILTER
1
-
20kHz
64 STEPS
REGISTERS
AND
STATE MACHINE
STAGE
TO SWITCHED
CAPACITOR
NETWORKS
SCK
CS
SI
SO
INT/HOLD
TEST
OSCIN
OSCOUT
VMID
CH0FB
CH0IN
CH1FB
CH1IN
V
DD
GND
POWER SUPPLY
AND
BIAS CIRCUITS
DIVIDER
PROGRAMMABLE
CH0NI
CH1NI
SAMPLE
AND HOLD
AND
ACTIVE
FULL WAVE
64 STEPS
GAIN
-
+
-
+
CLOCK
SPI
INTERFACE
Data Sheet
November 1998
File Number
4367.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
4-2
Pinout
HIP9011
(SOIC)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
V
DD
VMID
INTOUT
INT/HOLD
CS
SO
SI
SCK
TEST
CH1IN
CH1FB
CH0FB
CH0IN
GND
NC
NC
OSCIN
OSCOUT
CH0NI
CH1NI
Pin Descriptions
PIN
NUMBER
DESIGNATION
DESCRIPTION
1
V
DD
Five volt power input.
2
GND
This pin is tied to ground.
3
V
MID
This pin is connected to the internal mid-supply generator and is brought out for bypassing by a 0.022
F capacitor.
4
INTOUT
Buffered output of the integrator. Output signal is held by an internal Sample and Hold circuit when INT/HOLD is
low.
5, 6
NC
These pins are not internally connected. Do Not Use.
7
INT/HOLD
Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). This pin has an
internal pull down.
8
CS
A low input on this pin enables the chip to communicate over the SPI bus. This pin has an internal pull-up.
9
OSCIN
Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and
pin 10. To bias the inverter, a 1.0M
to 10M
resistor is usually connected between this pin and pin 10.
10
OSCOUT
Output of the inverter used for the oscillator. See pin 9 above.
11
SO
Output of the chip SPI data bus. This is a three-state output that is controlled via the SPI bus. The output is
placed in the high impedance state by setting CS high when the chip is not selected. This high impedance state
can also be programmed by setting the LSB of the prescaler word to 1. This will take precedence over CS. A 0
enables the active state. The Diagnostic Mode overrides these conditions.
12
SI
Input of the chip SPI data bus. Data length is eight bits. This pin has an internal pull-up.
13
SCK
Input from the SPI clock. Normally low, the data is transferred to the chip internal circuitry on the falling clock
edge. This pin has an internal pull up.
14
TEST
A low on this pin places the chip in the diagnostic mode. For normal operation this pin is tied high or left open.
This pin has an internal pull up.
15
CH1NI
Non-inverting input of Channel one.
16
CH1IN
Inverting input to channel one amplifier. A resistor is tied from this summing input to the transducer. A second
resistor is tied between this pin and pin 17, CH1FB to establish the gain of the amplifier.
17
CH1FB
Output of the channel one amplifier. This pin is used to apply feedback.
18
CH0FB
Output of the channel zero amplifier. This pin is used to apply feedback.
19
CH0IN
Inverting input to channel zero amplifier. Remainder same as channel one amplifier except feedback is applied
from pin 18.
20
CH0NI
Non-inverting input of Channel 0. Remainder the same as pin 16, except feedback is applied from terminal 18.
HIP9011
4-3
Absolute Maximum Ratings
Thermal Information
DC Logic Supply, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Output Voltage, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Max
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 125
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Power Dissipation, P
D
For T
A
= -40
o
C to 70
o
C . . . . . . . . . . . . . . . . . . . . . . . 400mW Max
For T
A
= 70
o
C to 125
o
C, Derate Linearly at . . . . . . . . . . 6mW/
o
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range, T
STG
. . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
At a Distance 1/16
1/32 inch, (1.59
0.79mm) from Case for
10s Max. (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= 5V
5%, GND = 0V, Clock Frequency 4MHz
0.1%, T
A
= -40
o
C to 125
o
C,
Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC ELECTRICAL SPECIFICATIONS
Quiescent Supply Current
I
DD
V
DD
= 5.25V, GND = 0V
-
5.0
8.0
mA
Midpoint Voltage, Pin 3
V
MID
V
DD
= 5.0V, I
L
= 2mA Source
2.3
2.45
2.55
V
Midpoint Voltage, Pin 3
V
MID
V
DD
= 5.0V, I
L
= 0mA
2.4
2.5
2.6
V
Low Input Voltage, Pins INT/HOLD, CS, SI, SCK
V
IL
-
-
30
% of V
DD
High Input Voltage, Pins INT/HOLD, CS, SI, SCK
V
IH
70
-
-
% of V
DD
Hysteresis voltage, Pins INT/HOLD, CS, SI, SCK
V
HYST
0.85
-
-
V
Internal Pull-Up Current
I Source CS, SI,
SCK, TEST
V
DD
= 5.0V, Measured at GND
-
50
-
A
Internal Pull-Down Current
I Sink,
INT/HOLD
V
DD
= 5.0V, Measured at V
DD
-
-50
-
A
Low Level Output, Pin SO
V
OL
I
SOURCE
= 1.6mA, V
DD
= 5.0V
0.01
-
0.30
V
High Level Output, Pin SO
V
OH
I
SINK
= 200
A, V
DD
= 5.0V
4.8
4.9
5.0
V
Three-State Leakage Pin SO
I
L
Measured at GND; V
DD
= 5.0V
-
-
10
A
Low Level Output, Pin 10, OSCOUT
V
OL
I
SOURCE
= 500
A; V
DD
= 5.0V
-
-
1.5
V
High Level Output, Pin 10, OSCOUT
V
OH
I
SINK
= -500
A; V
DD
= 5.0V
4.4
-
-
V
SPI BUS INTERFACE
AC Parametrics
CS Falling to SCLK Rising
t
CCH
10
-
-
ns
CS Rising to SCLK Falling
t
CCL
80
-
-
ns
SCLK Low
t
PWL
60
-
-
ns
SCLK High
t
PWH
60
-
-
ns
SCLK Falling to CS Rising
t
SCCH
60
-
-
ns
Data High Setup Time
t
SUH
20
-
-
ns
Data Low Setup Time
t
SUL
20
-
-
ns
Data High Hold Time
t
HH
10
-
-
ns
Data Low Hold Time
t
HL
10
-
-
ns
Min Time Between 2 Programmed Words
t
CSH
200
-
-
ns
CS Rising to INT/Hold Rising
t
CIH
8
-
-
s
HIP9011
4-4
INPUT AMPLIFIERS
CH0 and CH1 High Output Voltage
V
OUT
HI
I
SINK
= 100
A, V
DD
= 5.0V
4.7
4.9
-
V
CH0 and CH1 Low Output Voltage
V
OUT
LO
I
SOURCE
= 100
A; V
DD
= 5.0V
-
15
200
mV
Voltage Gain
A
CL
Input R = 47.5K, Feedback
R = 475k
+18
+20
+21
dB
ANTIALIASING FILTER
Response 1kHz to 20kHz, Referenced to 1kHz
BW
Test Mode
-
-0.5
-
dB
Attenuation at 180kHz, Referenced
to 1kHz
ATTEN
Test Mode
-10
-15
-
dB
PROGRAMMABLE FILTERS
Peak to Peak Voltage Output
V
OUT
Run Mode
3.5
4.0
-
V
P-P
Filters Q (Note 2)
Q
Run Mode
-
2.5
-
Q
PROGRAMMABLE GAIN AMPLIFIERS
Percent Amplifier Gain Deviation
%G
Run Mode
-
1
-
%
INTEGRATOR
Integrator Reset Voltage
V
RESET
Pin 4 Voltage at Start of
Integration
Cycle; V
DD
= 5.0V
75
125
175
mV
Integrator Droop after 500
s
V
DROOP
Hold Mode, Pin 7 = 0V,
V
DD
= 5.0V
Pin 4 set to 20% to 80% of V
DD
-
3
50
mV
DIFFERENTIAL CONVERTER
Differential to Single Ended Converter Offset
Voltage
DIFV
IO
By Design
-
0.1
-
mV
Change In Converter Output
DIFOUT
Run Mode, 500
A Sinking Load
to No Load Condition
-
1
10
mV
SYSTEM GAIN DEVIATION
Gain Deviation from "Ideal Equation" Correlation
Factor + 5.0% (Note 3)
V
OUT
-
V
RESET
Run Mode, maximum signal
output from Input Amplifier
<2.25V
P-P
, Equation Output X
0.95 + Device Reset Voltage;
For Total V
OUT
4.7V
-8%,
100mV
Equa-
tion
X 0.95
- V
RE-
SET
8%,
100mV
V
NOTES:
2. Q = fo/BW, where: fo = Center Frequency, BW = 3dB Bandwidth
3. Ideal Equation: INTOUT (Volts) = [V
IN
* G
IN
* G
PR
* G
BPF
* 1/
* (N/t
C
(ms)
*
f
Q
(kHz)) * G
DSE
] + V
RESET
Where: V
IN
= input signal amplitude (V
P-P
)
G
IN
= External Input Gain; GIN = R
F
/R
IN
G
PR
= Programmed Gain
G
BPF
= Gain of Bandpass Filter (2 for Ideal Case at Center)
t
INT
= Integration Time; t
INT
= N/f
Q
0.318 = 1/
N = Number of Cycles of Input Signal
f
Q
= Frequency of Input Signal
R
F
= Feedback Resistor Value
R
IN
= Signal Input Resistor Value
t
C
= Programmed Time Constant
G
DSE
= Gain of DSE Converter (2 for Ideal Case)
V
RESET
= Integrator Reset Voltage = 0.125V, Typ
Electrical Specifications
V
DD
= 5V
5%, GND = 0V, Clock Frequency 4MHz
0.1%, T
A
= -40
o
C to 125
o
C,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HIP9011
4-5
Timing Diagrams
FIGURE 1. SPI TIMING
B7
B6
B5
B4
B3
B2
B1
B0
SI
SCK
CS
t
CSCH
t
CSCF
t
PWH
t
PWL
t
SCCH
t
SUH
t
HH
INT/HOLD
t
CIH
B7
B6
B5
B4
B3
B2
B1
B0
SO
t
CSH
TABLE 1. SPI TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
t
CSCH
Minimum time from CS falling edge to SCK rising edge.
10ns
t
CSCF
Minimum time from CS falling edge to SCK falling edge.
80ns
t
PWL
Minimum time for the SCK low.
60ns
t
PWH
Minimum time for the SCK high.
60ns
t
SCCH
Minimum time from SCK falling after 8 bits to CS raising edge.
80ns
t
SUH
Minimum time from data high to falling edge of spiclk.
20ns
t
SUL
Minimum time from data low to falling edge of spiclk.
20ns
t
HH
Minimum time for data high after the falling edge of the spiclk.
10ns
t
HL
Minimum time for data low after the falling edge of the spiclk.
10ns
t
CIH
Minimum time after CS raises until INT/HOLD goes high.
8
s
t
CSH
Minimum time between programming 2 internal registers.
200ns
INT/HOLD
INTOUT
t1
t2
t3
t4
FIGURE 2. INTEGRATOR TIMING
TABLE 2. INTEGRATE/HOLD TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
t1
Maximum rise time of the INT/HOLD signal.
45ns
t2
Maximum time after INT/HOLD rises for INTOUT to begin to integrate.
20
s
t3
Maximum fall time of INT/HOLD signal.
45ns
t4
Typical time after INT/HOLD goes low before chip goes into hold state.
20
s
HIP9011
PDF 
ZIP