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Электронный компонент: ICS8731-01

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ICS8731-01 Preliminary Data Sheet
background image
8731CY-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 3, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
PRELIMINARY
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
11 differential 3.3V LVPECL outputs
Differential reference clock input pair
REF_CLK, nREF_CLK pair can accept the following
differential input levels: LVDS, LVPECL, LVHSTL, SSTL,
HCSL
Output frequency up to 650MHz
Maximum reference clock input frequency: 250MHz
Accepts any single-ended input signal with a resistor bias
on nCLK input
External feedback for zero delay capabilitiy
Output skew: 200ps (maximum)
Cycle-to-cycle jitter: 50ps (typical)
Full 3.3V operating supply
0C to 70C ambient operating temperature
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
MR
V
CCO
Q8
nQ8
Q9
nQ9
V
EE
Q10/QFB
nQ10/nQFB
V
CCO
FB_IN
nFB_IN
V
CCO
nQ3
Q3
nQ2
Q2
V
EE
nQ1
Q1
nQ0
Q0
V
CCO
nc
DIV_SEL2
DIV_SEL1
DIV_SEL0
V
CCA
V
EE
REF_CLK
nREF_CLK
FB_SEL1
FB_SEL0
V
CC
V
EE
nc
PLL_SEL
V
CCO
Q4
nQ4
Q5
nQ5
V
EE
Q6
nQ6
Q7
nQ7
V
CCO
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
G
ENERAL
D
ESCRIPTION
The ICS8731-01 is a low voltage, low skew,
1-to-11 Differential-to-3.3V LVPECL Clock Mul-
tiplier/Zero Delay Buffer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. With output frequencies up
to 650MHz the ICS8731-01 is targeted at high performance
clock applications. Along with a fully integrated PLL the
ICS8731-01 contains frequency configurable, differential out-
puts and external feedback inputs for multiplying clock fre-
quencies and regenerating clocks with "zero delay". Fre-
quency multiplication is achieved by utilizing the seperate
feedback and clock output dividers. The value of the multi-
plier is determined by the ratio of the feedback divider, M, to
the output divider, N. For multiplier values greater than 1, M
must be greater than N. For multiplier values less than 1, M
must be less than N. The zero delay mode is achieved with
M and N at equal values. The divide values of the clock and
feedback outputs are controlled by the DIV_SEL0:2 and
FB_SEL0:1 inputs, respectively. The ICS8731-01 accepts
any differential signal and translates it to differential 3.3V
LVPECL output levels.
ICS8731-01
HiPerClockSTM
,&6
PLL
0
1
2
4
6
8
1
2
4
6
8
Q0:Q9
nQ0:nQ9
Q10/FB_OUT
nQ10/nFB_OUT
100
000
001
010
011
00
01
10
11
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
DIV_SEL0
DIV_SEL1
DIV_SEL2
REF_CLK
nREF_CLK
FB_IN
nFB_IN
PLL_SEL
MR
FB_SEL1
FB_SEL0
background image
8731CY-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 3, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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background image
8731CY-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 3, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
PRELIMINARY
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
FOR
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background image
8731CY-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 3, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
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background image
8731CY-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 3, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
PRELIMINARY
T
ABLE
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HARACTERISTICS
,
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CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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5
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