2000 Fairchild Semiconductor Corporation
DS010202
www.fairchildsemi.com
March 1989
Revised August 2000
DM93L38
8-
Bit
Mult
i
p
le
Port
Regi
ste
r
DM93L38
8-Bit Multiple Port Register
General Description
The DM93L38 is an 8-bit multiple port register designed for
high speed random access memory applications where the
ability to simultaneously read and write is desirable. A com-
mon use would be as a register bank in a three address
computer. Data can be written into any one of the eight bits
and read from any two of the eight bits simultaneously. The
circuit uses TTL technology and is compatible with all TTL
families.
Features
s
Master/slave operation permitting simultaneous write/
read without race problems
s
Simultaneously read two bits and write one bit in any
one of eight bit positions
s
Readily expandable to allow for larger word sizes
Ordering Code:
Logic Symbol
V
CC
=
Pin 16
GND
=
Pin 8
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
DM93L38N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
A0A2
Write Address Inputs
DA
Data Input
B0B2
B Read Address Inputs
C0C2
C Read Address Inputs
CP
Clock Pulse Input (Active Rising Edge)
SLE
Slave Enable Input (Active LOW)
ZB
B Output
ZC
C Output
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2
DM93L38
Functional Description
The DM93L38 8-bit multiple port register can be consid-
ered a 1-bit slice of eight high speed working registers.
Data can be written into any one and read from any two of
the eight locations simultaneously. Master/slave operation
eliminates all race problems associated with simultaneous
read/write activity from the same location. When the clock
input (CP) is LOW data applied to the data input line (D
A
)
enters the selected master. This selection is accomplished
by coding the three write input select lines (A0A2) appro-
priately. Data is stored synchronously with the rising edge
of the clock pulse.
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0B2 and
C0C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (Z
B
and Z
C
).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The
data flows into the device, is demultiplexed according to
the state of the write address lines and is clocked into the
selected latch. The eight latches function as masters and
store the input data. The two output latches are slaves and
hold the data during the read operation. The state of each
slave is determined by the state of the master selected by
its associated set of read address inputs.
The method of parallel expansion is shown in Figure 1.
One DM93L38 is needed for each bit of the required word
length. The read and write input lines should be connected
in common on all of the devices. This register configuration
provides two words of n-bits each at one time, where n
devices are connected in parallel.
FIGURE 1. Parallel Expansion
3
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DM93L38
Logic Diagram
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4
DM93L38
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Note 2: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: I
CC
is measured with all outputs OPEN and all input grounded.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Norm
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.7
V
I
OH
HIGH Level Output Current
-
400
A
I
OL
LOW Level Output Current
4.8
mA
T
A
Free Air Operating Temperature
-
55
125
C
t
S
(H)
Setup Time HIGH or LOW
30
ns
t
S
(L)
D
A
to CP
22
t
H
(H)
Hold Time HIGH or LOW
0
ns
t
H
(L)
D
A
to CP
-
4.0
t
S
(H)
Setup Time HIGH or LOW
0
ns
t
S
(L)
A
n
to CP
0
t
H
(H)
Hold Time HIGH or LOW
0
ns
t
H
(L)
A
n
to CP
0
t
W
(H)
CP Pulse Width HIGH or LOW
40
ns
t
W
(L)
30
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 2)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
10 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max,
2.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW Level
V
CC
=
Min I
OL
=
Max
0.3
V
Output Voltage
V
IH
=
Min, V
IL
=
Max
I
I
Input Current @ Max Input Voltage
V
CC
=
Max, V
I
=
5.5V
1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.4V
50
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.3V
-
2
mA
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 3)
-
2.5
-
25
mA
I
CC
Supply Current
V
CC
=
Max (Note 4)
70
mA
5
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DM93L38
Switching Characteristics
V
CC
=
+
5.0V, T
A
=
+
25
C
Symbol
Parameter
C
L
=
15 pF
Units
Min
Max
t
PLH
Propagation Delay
68
ns
t
PHL
B
n
or C
n
or Z
n
95
t
PLH
Propagation Delay
70
ns
t
PHL
D
A
to Z
n
92
t
PLH
Propagation Delay
65
ns
t
PHL
CP to Z
n
57
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