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071701
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Power supply monitor resets processor when
V
CC
power loss occurs and holds processor in
reset during V
CC
ramp-up
Battery monitor checks remaining capacity
daily
Read and write access times as fast as 100 ns
Unlimited write cycle endurance
Typical standby current 50 A
Upgrade for 128k x 8 SRAM, EEPROM or
Flash
Lithium battery is electrically disconnected to
retain freshness until power is applied for the
first time
Optional industrial temperature range of
-40C to +85C, designated IND
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0-A16
- Address Inputs
DQ0-DQ7
- Data In/Data Out
CE
- Chip Enable
WE
- Write Enable
OE
- Output Enable
RST
- Reset Output
BW
- Battery Warning Output
V
CC
- Power (+3.3 Volts)
GND
- Ground
NC
- No Connect
DESCRIPTION
The DS1345W 3.3V 1024k Nonvolatile SRAM is a 1,048,576-bit, fully static, nonvolatile SRAM
organized as 131,072 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry, which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. Additionally, the DS1345W has dedicated circuitry for monitoring the
status of V
CC
and the status of the internal lithium battery. DS1345W devices in the PowerCap Module
package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a
complete Nonvolatile SRAM module. The devices can be used in place of 128k x 8 SRAM, EEPROM or
Flash components.
DS1345W
3.3V 1024k Nonvolatile SRAM
with Battery Monitor
www.maxim-ic.com
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14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
BW
A15
A16
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND V
BAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC PowerCap)
DS1345W
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READ MODE
The DS1345W executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 17 address inputs
(A
0
- A
16
) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
satisfied, then data access must be measured from the later occurring signal (
CE
or
OE
) and the limiting
parameter is either t
CO
for
CE
or t
OE
for
OE
rather than address access.
WRITE MODE
The DS1345W executes a write cycle whenever the
WE
and
CE
signals are in the active (low) state after
address inputs are stable. The later occurring falling edge of
CE
or
WE
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must
be kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time
(t
WR
) before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1345W provides full functional capability for V
CC
greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V
CC
without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become "don't care," and all outputs become high impedance. As V
CC
falls below approximately 2.5 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V
CC
rises above approximately 2.5 volts, the power
switching circuit connects external V
CC
to the RAM and disconnects the lithium energy source. Normal
RAM operation can resume after V
CC
exceeds 3.0 volts.
SYSTEM POWER MONITORING
The DS1345W has the ability to monitor the external V
CC
power supply. When an out-of-tolerance power
supply condition is detected, the NV SRAM warns a processor-based system of impending power failure
by asserting
RST
. On power up,
RST
is held active for 200ms nominal to prevent system operation
during power-on transients and to allow t
REC
to elapse.
RST
has an open-drain output driver.
BATTERY MONITORING
The DS1345W automatically performs periodic battery voltage monitoring on a 24-hour time interval.
Such monitoring begins within t
REC
after V
CC
rises above V
TP
and is suspended when power failure
occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1M test resistor for 1
second. During this 1 second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
BW
is asserted. Once asserted,
BW
remains active until the module is replaced.
The battery is still retested after each V
CC
power-up, however, even if
BW
is active. If the battery voltage
is found to be higher than 2.6V during such testing,
BW
is de-asserted and regular 24-hour testing
resumes.
BW
has an open-drain output driver.
DS1345W
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FRESHNESS SEAL
Each DS1345W is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level greater than V
TP
, the lithium
energy source is enabled for battery backup operation.
PACKAGES
The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control into a module base
along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap
Module package design allows a DS1345W device to be surface mounted without subjecting its lithium
backup battery to destructive high-temperature reflow soldering. After a DS1345W is reflow soldered, a
DS9034PC is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The
DS9034PC is keyed to prevent improper attachment. DS1345W module bases and DS9034PC
PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for
further information.
DS1345W
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ABSOLUTE MAXIMUM RATINGS*
Voltage On Any Pin Relative To Ground
-0.3V to +4.6V
Operating Temperature
0C to 70C, -40C to +85C for IND parts
Storage Temperature
-40C to +70C, -40C to +85C for IND parts
Soldering Temperature
260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Power Supply Voltage
V
CC
3.0
3.3
3.6
V
Logic 1
V
IH
2.2
V
CC
V
Logic 0
V
IL
0.0
0.4
V
DC ELECTRICAL CHARACTERISTICS (T
A
: See Note 10) (V
CC
= 3.3V
0.3V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage Current
I
IL
-1.0
+1.0
A
I/O Leakage Current
CE
V
IH
V
CC
I
IO
-1.0
+1.0
A
Output Current @ 2.2V
I
OH
-1.0
mA
14
Output Current @ 0.4V
I
OL
2.0
mA
14
Standby Current
CE
= 2.2V
I
CCS1
50
250
A
Standby Current
CE
= V
CC
-0.2V
I
CCS2
30
150
A
Operating Current
I
CCO1
50
mA
Write Protection Voltage
V
TP
2.8
2.9
3.0
V
CAPACITANCE
(T
A
= 25C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
C
IN
5
10
pF
Input/Output Capacitance
C
I/O
5
10
pF
DS1345W
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AC ELECTRICAL CHARACTERISTICS
(T
A
: See Note 10) (V
CC
=3.3V
0.3V)
DS1345W-100 DS1345W-150
PARAMETER
SYMBOL
MIN
MAX
MAX
MIN
UNITS
NOTES
Read Cycle Time
t
RC
100
150
ns
Access Time
t
ACC
100
150
ns
OE
to Output Valid
t
OE
50
70
ns
CE
to Output Valid
t
CO
100
150
ns
OE
or
CE
to Output Active
t
COE
5
5
ns
5
Output High Z
from Deselection
t
OD
35
35
ns
5
Output Hold from
Address Change
t
OH
5
5
ns
Write Cycle Time
t
WC
100
150
ns
Write Pulse Width
t
WP
75
100
ns
3
Address Setup Time
t
AW
0
0
ns
Write Recovery Time
t
WR1
t
WR2
5
20
5
20
ns
12
13
Output High Z from
WE
t
ODW
35
35
ns
5
Output Active from
WE
t
OEW
5
5
ns
5
Data Setup Time
t
DS
40
60
ns
4
Data Hold Time
t
DH1
t
DH2
0
20
0
20
ns
12
13
READ CYCLE
SEE NOTE 1
DS1345W
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WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1345W
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POWER-DOWN/POWER-UP CONDITION
BATTERY WARNING DETECTION
SEE NOTE 14
DS1345W
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POWER-DOWN/POWER-UP TIMING
(T
A
: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
1.5
s
11
V
CC
slew from V
TP
to 0V
t
F
150
s
V
CC
Fail Detect to
RST
Active
t
RPD
15
s
14
V
CC
slew from 0V to V
TP
t
R
150
s
V
CC
Valid to
CE
and
WE
Inactive
t
PU
2
ms
V
CC
Valid to End of Write
Protection
t
REC
125
ms
V
CC
Valid to
RST
Inactive
t
RPU
150
200
350
ms
14
V
CC
Valid to
BW
Valid
t
BPU
1
s
14
BATTERY WARNING TIMING
(T
A
: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Battery Test Cycle
t
BTC
24
hr
Battery Test Pulse Width
t
BTPW
1
s
Battery Test to
BW
Active
t
BW
1
s
(T
A
= 25C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data
Retention Time
t
DR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a read cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4. t
DS
is measured from the earlier of
CE
or
WE
going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output
buffers remain in a high impedance state during this period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high impedance state during this period.
8. If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS1345W has a built-in switch that disconnects the lithium source until V
CC
is first applied by
the user. The expected t
DR
is defined as accumulative time in the absence of V
CC
starting from the
time power is first applied by the user.
DS1345W
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10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0C to 70C. For industrial products (IND), this range is -40C to
+85C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on V
CC
.
12. t
WR1
and t
DH1
are measured from
WE
going high.
13. t
WR2
and t
DH2
are measured from
CE
going high.
14.
RST
and
BW
are open-drain outputs and cannot source current. External pullup resistors should be
connected to these pins for proper operation. Both pins will sink 10mA.
15. DS1345 PowerCap modules are pending U.L review. Contact the factory for status.
DC TEST CONDITIONS
Outputs Open
Cycle = 200ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 to 2.7V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1345 W P - SSS - III
Operating Temperature Range
blank: 0
to 70
IND: -40
to +85C
Access Speed
100: 100ns
150: 150ns
P: 34-pin PowerCap Module
DS1345W
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DS1345W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
INCHES
PKG
DIM
MIN
NOM
MAX
A
0.920
0.925
0.930
B
0.980
0.985
0.990
C
-
-
0.080
D
0.052
0.055
0.058
E
0.048
0.050
0.052
F
0.015
0.020
0.025
G
0.020
0.025
0.030
DS1345W
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DS1345W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP
INCHES
PKG
DIM
MIN
NOM
MAX
A
0.920
0.925
0.930
B
0.955
0.960
0.965
C
0.240
0.245
0.250
D
0.052
0.055
0.058
E
0.048
0.050
0.052
F
0.015
0.020
0.025
G
0.020
0.025
0.030
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that
PowerCap Module bases experience one
pass through solder reflow oriented
label-side up (live-bug).
Hand soldering and touch-up
Do not touch soldering iron to leads for
more than 3 seconds. To solder, apply
flux to the pad, heat the lead frame pad
and apply solder. To remove part, apply
flux, heat pad until solder reflows, and
use a solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a
68-pin PLCC socket, attach a
DS9034PC PowerCap to a module base
then insert the complete module into the
socket one row of leads at a time,
pushing only on the corners of the cap.
Never apply force to the center of the
device. To remove from a socket, use a
PLCC extraction tool and ensure that it
does not hit or damage any of the
module IC components. Do not use any
other tool for extraction.
DS1345W
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RECOMMENDED POWERCAP MODULE LAND PATTERN
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
INCHES
PKG
DIM
MIN
NOM
MAX
A
-
1.050
-
B
-
0.826
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