Clock Buffer/Driver
W40S11-23
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 28, 1999 rev. **
Features
Thirteen skew-controlled CMOS clock outputs
(SDRAM0:12)
Supports three SDRAM DIMMs
Ideal for high-performance systems designed around
Intel's latest chip set
I
2
C serial configuration interface
Clock Skew between any two outputs is less than 250 ps
1- to 5-ns propagation delay
DC to 133-MHz operation
Single 3.3V supply voltage
Low power CMOS design packaged in a 28-pin, 300-mil
SOIC (Small Outline Integrated Circuit)
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output
clock buffer. Output buffer impedance is approximately 15
,
which is ideal for driving SDRAM DIMMs.
Key Specifications
Supply Voltages:........................................... V
DD
= 3.3V5%
Operating Temperature:.................................... 0C to +70C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................V
DD
+ 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns
Output Edge Rate:.............................................. >1.5 V/ns
Output Clock Skew: .................................................. 250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance: ...............................................15
typical
Output Type: ................................................ CMOS rail-to-rail
Pin Configuration
SOIC
Block Diagram
Note:
1.
Internal pull-up resistor of 250K on SDATA and SCLOCK inputs
(not CMOS level).
[1]
[1]
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM0
Serial Port
SCLOCK
SDATA
Device Control
BUF_IN
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDATA
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM7
SDRAM6
GND
GND
SCLOCK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
W40S11-23
2
Functional Description
Output Drivers
The W40S11-23 output buffers are CMOS type which deliver
a rail-to-rail (GND to V
DD
) output voltage swing into a nominal
capacitive load. Thus, output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15
.
Operation
Data is written to the W40S11-23 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
SDRAM0:12
2, 3, 6, 7, 10,
11, 18, 19,
22, 23, 26,
27, 12
O
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to
within 250 ps of each other.
BUF_IN
9
I
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
SDATA
14
I/O
I
2
C Data input: Data should be presented to this input as described in the I
2
C section
of this data sheet. Internal 250-k
pull-up resistor.
SCLOCK
15
I
I
2
C clock input: The I
2
C data clock should be presented to this input as described in
the I
2
C section of this data sheet. Internal 250-k
pull-up resistor.
VDD
1, 5, 13, 20,
24, 28
P
Power Connection: Power supply for core logic and output buffers. Connected to 3.3V
supply.
GND
4, 8, 16, 17,
21, 25
G
Ground Connection: Connect all ground pins to the common system ground plane.
Table 1. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W40S11-23 to accept the bits in Data Bytes 06 for in-
ternal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W40S11-23
is 11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Code
Don't Care
Unused by the W40S11-23, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
3
Byte Count
Don't Care
Unused by the W40S11-23, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
4
Data Byte 0
Refer to Table 2
The data bits in these bytes set internal W40S11-23 registers that control
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 2, Data Byte Serial Configuration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
Don't Care
Refer to Cypress Frequency Timing Generators.
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
W40S11-23
3
Writing Data Bytes
Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7.
Table 2 gives the bit formats for registers located in Data Bytes
06.
Note:
2.
At power-up all SDRAM outputs are enabled and active. Program Reserved bits to a "0."
Table 2. Data Bytes 02 Serial Configuration Map
[2]
Bit(s)
Affected Pin
Control Function
Bit Control
Pin No.
Pin Name
0
1
Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
11
SDRAM5
Clock Output Disable
Low
Active
6
10
SDRAM4
Clock Output Disable
Low
Active
5
N/A
Reserved
(Reserved)
-
-
4
N/A
Reserved
(Reserved)
-
-
3
7
SDRAM3
Clock Output Disable
Low
Active
2
6
SDRAM2
Clock Output Disable
Low
Active
1
3
SDRAM1
Clock Output Disable
Low
Active
0
2
SDRAM0
Clock Output Disable
Low
Active
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
27
SDRAM11
Clock Output Disable
Low
Active
6
26
SDRAM10
Clock Output Disable
Low
Active
5
23
SDRAM9
Clock Output Disable
Low
Active
4
22
SDRAM8
Clock Output Disable
Low
Active
3
N/A
Reserved
(Reserved)
-
-
2
N/A
Reserved
(Reserved)
-
-
1
19
SDRAM7
Clock Output Disable
Low
Active
0
18
SDRAM6
Clock Output Disable
Low
Active
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
N/A
Reserved
(Reserved)
-
-
6
12
SDRAM12
Clock Output Disable
Low
Active
5
N/A
Reserved
(Reserved)
--
--
4
N/A
Reserved
(Reserved)
--
--
3
N/A
Reserved
(Reserved)
--
--
2
N/A
Reserved
(Reserved)
--
--
1
N/A
Reserved
(Reserved)
--
--
0
N/A
Reserved
(Reserved)
--
--
W40S11-23
4
How To Use the Serial Data Interface
Electrical Requirements
Figure 1 illustrates electrical characteristics for the serial inter-
face bus used with the W40S11-23. Devices send data over
the bus with an open drain logic output that can (a) pull the bus
line LOW, or (b) let the bus default to logic 1. The pull-up resis-
tor on the bus (both clock and data lines) establish a default
logic 1. All bus devices generally have logic inputs to receive
data.
Although the W40S11-23 is a receive-only device (no data
write-back capability), it does transmit an "acknowledge" data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration to-
tal bus line capacitance.
DATA IN
DATA OUT
N
CLOCK IN
C L O C K O U T
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
S D C L K
SDATA
SERIAL BUS CLOCK LINE
SERIAL BUS DATA LINE
N
DATA IN
DATA OUT
CLOCK IN
C L O C K D E V I C E
(SERIAL BUS SLAVE RECEIVER)
S C L O C K
SDATA
N
~ 2k
~ 2k
V D D
V D D
Figure 1. Serial Interface Bus Electrical Characteristics
W40S11-23
5
Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a "start bit" as shown in Figure
3. A "stop bit" signifies that a transmission has ended.
As stated previously, the W40S11-23 sends an "acknowledge"
pulse after receiving eight data bits in each byte as shown in
Figure 4.
SDATA
S C L O C K
Valid
Data
Bit
Change
of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
S D A T A
S C L O C K
Start
Bit
Stop
Bit
Figure 3. Serial Data Bus Start and Stop Bit
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