Central
Semiconductor Corp.
TM
PROCESS
CP117
Power Transistor
NPN - Darlington Chip
PRINCIPAL DEVICE TYPES
2N6043
2N6044
2N6045
2N6301
Process
EPITAXIAL BASE
Die Size
111 X 111 MILS
Die Thickness
10 MILS
Base Bonding Pad Area
20 X 30 MILS
Emitter Bonding Pad Area
20 X 26 MILS
Top Side Metalization
Al - 30,000
Back Side Metalization
Au/Cr/Ni/Au - Ni-6,000, Au-6,000
PROCESS DETAILS
R6 (1 -August 2002)
GEOMETRY
BACKSIDE COLLECTOR
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
GROSS DIE PER 5 INCH WAFER
910
Central
Semiconductor Corp.
TM
Central
Semiconductor Corp.
TM
PROCESS
CP117
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R6 (1 -August 2002)
Central
Semiconductor Corp.
TM
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