1
Features
Pixel Size: 11 m x 13 m (13 m Pitch)
High Data Output Rate: 20 MHz
High Responsivity and Resolution Over a Wide Spectral Range: from Blue (400 nm) up
to Near Infrared (1,100 nm)
Low Dark Signal and Improved Uniformity
Low Temporal Noise and High Dynamic Range: Over 6000/1
Ease and Flexibility of Operation:
Only Two External Basic Drive Clocks
Choice of Internal or External Sampling and Reset
28-lead DIL Package
Available with Standard Window or Antireflective Window in the Bandwidth 450 to
750 nm
Pin Identification
Pin Number
Symbol
Designation
2
V
OSA
Video Output Signal A (Odd Channel)
3
ECHA
A Sample-and-hold Gate Input Channel
4
S
ECHA
A Internal Sampling Clock Output Channel
5
RA
A External Reset Clock Input Channel
9
V
DD
Output Amplifier Drain And Internal Logic Supply
10
TP3
Test Point 3
11
TP2
Test Point 2
12
VT
Register and Photosensitive Zone DC Bias
13
TP1
Test Point 1
14, 15, 28
V
SS
Substrate Bias (Ground)
16
V
INH
Internal Sampling Clock Inhibiting Input (Dc Bias)
18
P
Transfer Clock
19
T
Register Transport Clock
20
V
GS
Output Gate DC Bias
21
RB
B External Reset Clock Output Channel
24
S
ECHB
B Internal Sampling Clock Output Channel
25
ECHB
B Sample-and-hold Gate Input Channel
26
V
OSB
Video Output Signal B (Even Channel)
27
V
DR
Reset DC Bias
1, 6, 7, 8, 17, 22, 23
DNC
Do not Connect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DNC
VOSA
ECHA
S
ECHA
RA
DNC
DNC
DNC
VDD
TP3
TP2
VT
TP1
VSS
VSS
VDR
VOSB
ECHB
S
ECHB
DNC
DNC
RB
VGS
T
P
DNC
VINH
VSS
Linear CCD
Image Sensor
(2048 Pixels)
TH7841A
Rev. 1998AIMAGE05/02
2
TH7841A
1998AIMAGE05/02
T
Operating Range
Operating range defines the temperature limits between which the functionality is guar-
anteed: 0C to 70C.
Operating
Precautions
Shorting the video output to V
SS
to V
DD
, even temporarily, can permanently damage the
output amplifier.
Absolute Maximum Ratings*
Storage Temperature ..................................... -55C to +150C
*NOTICE:
Stresses above those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent
device failure. Functionality at or above these
limits is not implied. Exposure to absolute maxi-
mum ratings for extended periods may affect
device reliability.
Operating Temperature ........................................0C to +70C
Thermal Cycling..........................................................15C/mn
Maximum Voltages:
Pins: 3, 5, 9, 10, 11, 13,
16, 19, 20, 21, 25, 27........................................-0.3V to +18V
Pins: 12. 18 ......................................................-0.3V to +16V
Pins: 14, 15, 28 ................................................................. 0V
3
TH7841A
1998AIMAGE05/02
Operating Conditions (T = 25C)
Notes:
1. It is recommended to maintain V
DR
at V
DD
- 2V.
2. V
T
nominal =
3. No use for operation For testing purpose only.
Basic Internal
Configuration
Note:
1. Make the straps as short as possible to avoid any parasitic coupling to these connec-
tions. The load capacitance introduced by the strap should not exceed 5 pF.
Table 1. DC Characteristics
Parameter
Symbol
Values
Unit
Note
Min
Typ
Max
Output Amplifier Drain Supply
V
DD
14
15
16
V
Reset DC Bias
V
DR
12
13
14.5
V
(1)
Output Gate DC Bias
V
GS
5.5
6
6.5
V
Photosensitive Zone and
Register DC Bias
V
T
6
6.5
7
V
(2)
Substrate Bias
V
SS
0.0
0.0
Test Point 1
TP1
V
DD
V
(3)
Test Points 2 and 3
TP2, TP3
V
SS
V
(3)
V
T
(
)high
V
T
(
)low
+
2
------------------------------------------------------------
5%
S
ECHA
and
RA
internal to TH7841A
S
ECHB
and
RB
Table 2. Selection of Nominal Mode
Option
Implementation
Note
Internal Sampling
V
INH
(16) Connected to V
SS
S
ECHA
(4) and
ECHA
(3) Strapped
S
ECHB
(24) and
ECHB
(25) Strapped
(1)
Internal Reset
RA
(5) and
RB
(21) Connected to VDD
4
TH7841A
1998AIMAGE05/02
Figure 1. Timing Diagram -- Clocks and Video Output Timing Diagram in Internal Sampling Mode
Note:
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal if such
spurious negative transients are present, they can be suppressed by inserting a serial resistor of appropriate value (typically
20 to 100
) in the corresponding driver output.
Table 3. Drive Clock Characteristics (see Figure 1)
Parameter
Symbol
Logic
Values
Unit
Note
Min
Typ
Max
Transfer Clock
P
T
High
12
13
14
V
(1)
Register Transport Clock
Low
0.0
0.4
0.6
Register Transport Clock
Capacitance
C
T
800
1200
pF
Transfer Clock Capacitance
C
P
200
300
pF
5
TH7841A
1998AIMAGE05/02
Notes:
1. V
OS
= average video output voltage. Measurement excludes first and last pixels.
2. F
S
= 2F
T
. The minimum clock frequency is limited by the increase in dark signal.
Electro-optical
Performance
General measurement conditions: T
C
= 25C; T
i
= 1 ms;
F
T
= 2.5 MHz.
Light source: tungsten filament lamp (2854 K) + BG 38 filter (2 mm thick) + F/3.5 aper-
ture. The filter limits the spectrum to 700 nm; in these conditions, 1 J/cm
2
corresponds
to 3.5 lux.s.
Typical operating conditions; internal clock mode (see Table 2).
First and last pixels, as well as reference elements, are excluded from the specification.
Measurements taken on each output in succession.
Table 4. Static and Dynamic Electrical Characteristics
Parameter
Symbol
Values
Unit
Note
Min
Typ
Max
DC Output Level
V
REF
8
10
12
V
Output Impedance
Z
S
500
Register Single-stage Transfer Efficiency
CTE
99.992
99.998
%
V
OS
= 1V
(1)
Max. Data Output Frequency
F
S
max.
12
20
MHz
(2)
Input Current on Pins: 3, 5, 10,11,12, 13,
18, 19, 20, 21, 25
Ie
2
A
Ve = 15V
All other pins: 0V
Peak Current Sink on
T
Clock
(I
T
)
P
500
mA
t
rise
= 15 ns
Peak Current Sink on
P
Clock
(I
P
)
P
125
mA
t
rise
= 15 ns
Output Amplifier Drain Supply Current
I
DD
17
mA
V
INH
= 0V
V
DD
= 15V
Static Power Dissipation
P
D
255
300
mW
V
INH
= 0V
V
DD
= 15V
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