1
Features
Available in Gate Array or Embedded Array
High-speed, 150 ps Gate Delay, 2-input NAND, FO = 2 (nominal)
Up to 2.7 Million Used Gates and 976 Pins
0.35 Geometry in up to Four-level Metal
System-level Integration Technology
Cores: ARM7TDMI
TM
RISC Microprocessor; AVR
RISC Microcontroller;
OakDSPCore
TM
, Teak
TM
and PalmDSPCore
TM
Digital Signal Processors; 10/100
Ethernet MAC, USB, 1394, 1284, CAN Cores and Other Assorted Processor
Peripherals
Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs, and PORs
Soft Macro Memory: Gate Array
SRAM -- ROM -- DPSRAM -- FIFO
Hard Macro Memory: Embedded Array
SRAM -- ROM -- DPSRAM -- FIFO -- E
2
-- Flash
I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 20 mA
@3.3V; 2.5V Native I/O, 3.3V Native I/O, 5.0V Tolerant/Compliant I/O
Description
The ATL35 Series ASIC family is fabricated on a 0.35 CMOS process with up to four
levels of metal. This family features arrays with up to 2.7 million routable gates and
976 pins. The high density and high pin count capabilities of the ATL35 family, coupled
with the ability to add embedded microprocessor cores, DSP engines and memory on
the same silicon, make the ATL35 series of ASICs an ideal choice for system-level
integration.
Figure 1. ATL35 Gate Array ASIC
Figure 2. ATL35 Embedded Array ASIC
Standard
Gate Array
Architecture
Analog
ASIC
ATL35 Series
Rev. 0802FASIC05/02
3
0802FASIC05/02
Design
Atmel supports several major software systems for design with complete cell libraries,
as well as utilities for netlist verification, test vector verification and accurate delay
simulations.
Design Flow and
Tools
Atmel's ASIC design flow is structured to allow the designer to consolidate the greatest
number of system components onto the same silicon chip, using widely available third-
party design tools. Atmel's cell library reflects silicon performance over extremes of tem-
perature, voltage and process, and includes the effects of metal loading, interlevel
capacitance, and edge rise and fall times. The design flow includes clock tree synthesis
to customer-specified skew and latency goals. RC extraction is performed on the final
design database and incorporated into the timing analysis.
The ASIC Design Flow, shown on page 4, provides a pictorial description of the typical
interaction between Atmel's design staff and the customer. Atmel will deliver design kits
to support the customer's synthesis, verification, floorplanning and scan insertion activi-
ties. Leading-edge tools from vendors such as Synopsys and Cadence are fully
supported in our design flow. In the case of an embedded array design, Atmel will con-
duct a design review with the customer to define the partition of the embedded array
ASIC and to define the location of the memory blocks and/or cores so an underlayer lay-
out model can be created.
Following database acceptance, automated test pattern generation (ATPG) is per-
formed, if required, on scan paths using Synopsys tools; the design is routed; and post-
route RC data is extracted. After post-route verification and a final design review, the
design is taped out for fabrication.
Table 2. Design Systems Supported
System
Tools
Version
Cadence
Design
Systems, Inc.
Opus
TM
Schematic and Layout
NC Verilog
TM
Verilog Simulator
Pearl
TM
Static Path
Verilog-XL
TM
Verilog Simulator
BuildGates
TM
Synthesis (Ambit)
4.46
3.3-s008
4.3-s095
3.3-s006
4.0-p003
Mentor
Graphics
ModelSim
Verilog and VHDL (VITAL) Simulator
Leonardo Spectrum
TM
Logic Synthesis
5.5e
2001.1d
Synopsys
TM
Design Compiler
TM
Synthesis
DFT Compiler 1-Pass Test Synthesis
BSD Compiler Boundary Scan Synthesis
TetraMax
Automatic Test Pattern Generation
PrimeTime
TM
Static Path
VCS
TM
Verilog Simulator
Floorplan Manager
TM
01.01-SP1
01.08-SP1
01.08-SP1
01.08
01.08-SP1
5.2
01.08-SP1
Novas
Software, Inc.
Debussy
5.1
Silicon
Perspective
TM
First Encounter
v2001.2.3
5
0802FASIC05/02
Pin Definition
Requirements
The corner pads are reserved for Power and Ground only. All other pads are fully pro-
grammable as Input, Output, Bidirectional, Power or Ground. When implementing a
design with 5V compliant buffers, an appropriate number of pad sites must be reserved
for the VDD5 pins, which are used to distribute 5V power to the compliant buffers.
Design Options
Logic Synthesis
Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports
Synopsys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats,
Verilog and VHDL, Atmel's preferred HDL format for ASIC design is Verilog.
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