Document Outline

• ARM966E-S (Rev 1) Technical Reference Manual
• Preface
• 1 Introduction
  • 1.1 About the ARM966E-S
  • 1.2 Microprocessor block diagram
• 2 Programmer�s Model
  • 2.1 About the programmer�s model
  • 2.2 About the ARM9E-S programmer�s model
    • 2.2.1 Data Abort model
  • 2.3 ARM966E-S CP15 registers
    • 2.3.1 CP15 register map summary
    • 2.3.2 Register 0, ID code
    • 2.3.3 Register 1, Control register
      • Bit 15, Configure disable loading TBIT
      • Bit 13, Alternate vectors select
      • Bit 12, Instruction SRAM enable
      • Bit 7, Endian
      • Bit 3, Write buffer enable
      • Bit 2, Data SRAM enable
    • 2.3.4 Register 7, Core control
      • Wait for interrupt
      • Drain write buffer
    • 2.3.5 Register 13, Trace process identifier
    • 2.3.6 Register 15, Test
      • Trace control register
      • BIST control register
• 3 Memory Map
  • 3.1 About the ARM966E-S memory map
  • 3.2 Tightly-coupled SRAM address space
  • 3.3 Bufferable write address space
• 4 Tightly-coupled SRAM
  • 4.1 ARM966E-S SRAM requirements
  • 4.2 SRAM stall cycles
  • 4.3 Enabling the SRAM
    • 4.3.1 Using INITRAM input pin
      • Reset with INITRAM LOW
      • Reset with INITRAM HIGH
    • 4.3.2 Using CP15 control register
      • Enabling the I-SRAM
      • Disabling the I-SRAM
      • Enabling the D-SRAM
      • Disabling the D-SRAM
  • 4.4 ARM966E-S SRAM wrapper
    • 4.4.1 Example SRAM interfaces
      • ONESEGX32
      • FOURSEGX32
      • FOURSEGX8
• 5 Direct Memory Access (DMA)
  • 5.1 About the DMA interface
    • 5.1.1 Single-port RAM DMA solution
    • 5.1.2 Dual-port RAM DMA solution
  • 5.2 Timing interface
    • 5.2.1 Single-port RAM reads
    • 5.2.2 Single-port RAM writes
    • 5.2.3 Dual-port RAM reads
    • 5.2.4 Dual-port RAM writes
    • 5.2.5 Mixed read and writes
  • 5.3 DMAENABLE setup and hold cycles
  • 5.4 Summary of signal behavior
• 6 Bus Interface Unit
  • 6.1 About the BIU and write buffer
  • 6.2 Write buffer operation
    • 6.2.1 Committing write data to the write buffer
    • 6.2.2 Draining write data from the write buffer
      • Natural write buffer drain
      • Enforced write buffer drain
      • AHB read access requested
      • Drain write buffer instruction
    • 6.2.3 Enabling the write buffer
    • 6.2.4 Disabling the write buffer
  • 6.3 AHB bus master interface
    • 6.3.1 Overview of AHB
    • 6.3.2 ARM966E-S transfer descriptions
      • Burst transfers
      • Bus request
      • Sequential instruction fetch
      • Back-to-back LDR or STR accesses
      • Simultaneous instruction and data request
      • STM timing
      • LDM timing
      • STM followed by instruction fetch
      • LDM followed by instruction fetch
      • STM crossing a 1KB boundary
      • LDM crossing a 1KB boundary
      • SWP instruction
  • 6.4 AHB clocking
    • 6.4.1 CLK to HCLK skew
      • Clock tree insertion at top level
      • Hierarchical clock tree insertion
• 7 Coprocessor Interface
  • 7.1 About the coprocessor interface
    • 7.1.1 Synchronizing the external coprocessor pipeline
    • 7.1.2 External coprocessor clocking
  • 7.2 LDC/STC
    • 7.2.1 Coprocessor handshake states
    • 7.2.2 Coprocessor handshake encoding
    • 7.2.3 Multiple external coprocessors
  • 7.3 MCR/MRC
  • 7.4 Interlocked MCR
  • 7.5 CDP
  • 7.6 Privileged instructions
  • 7.7 Busy-waiting and interrupts
• 8 Debug Support
  • 8.1 About the debug interface
    • 8.1.1 Stages of debug
    • 8.1.2 Clocks
  • 8.2 Debug systems
    • 8.2.1 The debug host
    • 8.2.2 The protocol converter
    • 8.2.3 ARM966ES debug target
  • 8.3 ARM966E-S scan chain 15
  • 8.4 Debug interface signals
    • 8.4.1 Entry into debug state on breakpoint
    • 8.4.2 Breakpoints and exceptions
    • 8.4.3 Watchpoints
    • 8.4.4 Watchpoints and exceptions
    • 8.4.5 Debug request
    • 8.4.6 Actions of the ARM9ES in debug state
  • 8.5 ARM9ES core clock domains
  • 8.6 Determining the core and system state
  • 8.7 About the EmbeddedICE-RT
  • 8.8 Disabling EmbeddedICE-RT
  • 8.9 The debug communications channel
    • 8.9.1 Debug communication channel registers
    • 8.9.2 Debug communications channel status register
    • 8.9.3 Communications channel monitor mode debug status register
    • 8.9.4 Communications via the communications channel
      • Sending a message to the debugger
      • Receiving a message from the debugger
  • 8.10 Monitor mode debug
  • 8.11 Debug additional reading
• 9 Embedded Trace Macrocell Interface
  • 9.1 About the ETM interface
  • 9.2 Enabling the ETM interface
  • 9.3 ARM966E-S trace support features
    • 9.3.1 FIFOFULL
    • 9.3.2 Register 15, trace control register
    • 9.3.3 Register 1, Trace process identifier
• 10 Test Support
  • 10.1 About the ARM966E-S test methodology
  • 10.2 Scan insertion and ATPG
    • 10.2.1 ARM966E-S INTEST wrapper
  • 10.3 BIST of tightly-coupled SRAM
    • 10.3.1 BIST control register
    • 10.3.2 BIST address and general registers
    • 10.3.3 Pause modes
      • Auto pause
      • User pause
• 11 Instruction cycle timings
  • 11.1 Introduction to instruction cycle timings
  • 11.2 When stall cycles do not occur
  • 11.3 Tightly-coupled SRAM cycles
  • 11.4 AHB memory access cycles
    • 11.4.1 Synchronization penalty
    • 11.4.2 AHB transfer types
  • 11.5 Interrupt latency calculation
• Appendix A Signal Descriptions
  • A.1 Signal properties and requirements
  • A.2 Clock interface signals
  • A.3 AHB signals
  • A.4 Coprocessor interface signals
  • A.5 Debug signals
  • A.6 Miscellaneous signals
  • A.7 ETM interface signals
  • A.8 INTEST wrapper signals
  • A.9 DMA Signals
• Appendix B AC Parameters
  • B.1 Timing diagrams
  • B.2 AC timing parameter definitions
• Appendix C SRAM Stall Cycles
  • C.1 About SRAM stall cycles
    • C.1.1 Read-follows-write
    • C.1.2 Additional Instruction SRAM stalls
      • Simultaneous instruction fetch, data read
      • Data read
      • Data read followed by instruction fetch
      • Simultaneous instruction fetch, data write
      • I-SRAM data write followed by instruction fetch
      • I-SRAM write followed by instruction fetch, data write
      • I-SRAM write followed by instruction fetch, data read
• Index