The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three ...
The SN74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high- ...
Oct 19, 2011 · The. 74LVC138A can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining ...
The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three ...
ESD Protection Exceeds 2000 V Per. MIL-STD-883, Method 3015; Exceeds 200 V. Using Machine Model (C = 200 pF, R = 0). • Operates From 2 V to 3.6 V.
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Sep 20, 2021 · The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).
[PDF] 74LVC138A 3-to-8 line decoder/demultiplexer ... - Futurlec
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Apr 28, 1998 · The 74LVC138A is a low-voltage, low-power, high-performance. Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The ...
74LVC138A. Obsolete. 3 LINE TO 8 LINE DECODER. Jump to Page Section: Overview; Design & Development; Product Options; Support.
Features. Accepts Three Binary Weighted Address Inputs and When Enabled Provides Output Accordingly; Three Enable Inputs; 5V Tolerant Input/Outputs ...
74LVC138 Datasheet. Part #: HD74LVC138. Datasheet: 37Kb/8P. Manufacturer: Hitachi Semiconductor. Description: 3-to-8-line Decoder / Demultiplexer.