Publication Release Date: April 13, 2005
- I -
Revision 1.1
W83176R-735
Data Sheet
WINBOND
3 DIMM DDR ZERO
DELAY BUFFER
FOR
SIS CHIPSET
W83176R-735
- II -
Table of Contents-
1.
GENERAL DESCRIPTION ......................................................................................................... 1
2.
FEATURES ................................................................................................................................. 1
3.
PIN CONFIGURATION ............................................................................................................... 1
4.
BLOCK DIAGRAM ...................................................................................................................... 2
5.
PIN DESCRIPTION..................................................................................................................... 2
5.1
Clock Outputs ................................................................................................................. 3
5.2
Power Pins...................................................................................................................... 3
6.
REGISTER 0 ~ REGISTER 4 RESERVED ................................................................................ 4
6.1
Register 5: Output Control (1 = Active, 0 = Inactive) (Default = FFH)............................ 4
6.2
Register 6: Output Control (1 = Active, 0 = Inactive) (Default = FFH)............................ 4
7.
ACCESS INTERFACE ................................................................................................................ 5
7.1
Block Write Protocol ....................................................................................................... 5
7.2
Block Read Protocol ....................................................................................................... 5
7.3
Byte Write Protocol ......................................................................................................... 5
7.4
Byte Read Protocol......................................................................................................... 5
8.
SPECIFICATIONS ...................................................................................................................... 6
8.1
Absolute Maximum Ratings ............................................................................................ 6
8.2
A.C. Characteristics ........................................................................................................ 6
8.3
D.C. Characteristics........................................................................................................ 6
9.
ORDERING INFORMATION....................................................................................................... 6
10.
HOW TO READ THE TOP MARKING........................................................................................ 7
11.
PACKAGE DRAWING AND DIMENSIONS................................................................................ 8
12.
REVISION HISTORY .................................................................................................................. 9
W83176R-735
Publication Release Date: April 13, 2005
- 1 -
Revision 1.1
1. GENERAL DESCRIPTION
The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735
can support 3 D.D.R. DRAM DIMMs.
The W83176R-735 provides I
2
C serial bus interface to program the registers to enable or disable each
clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply.
2. FEATURES
Zero-delay clock outputs
Feedback pins for synchronous
Supports up to 3 D.D.R. DIMMs
One pairs of additional outputs for feedback
Low Skew outputs (<100 pS)
Supports 400 MHz D.D.R. SDRAM
I
2
C 2-Wire serial interface and supports Byte or Block Date RW
Packaged in 48-pin SSOP
3. PIN CONFIGURATION
G N D 1
48 G N D
C LK C 0 2
47 C LK C 5
C LK T0 3
46 C LK T5
V D D 4
45 V D D
C LK T1 5
44 C LK T6
C LK C 1 6
43 C LK C 6
G N D 7
42 G N D
G N D 8
41 G N D
C LK C 2 9
40 C LK C 7
C LK T2 10
39 C LK T7
V D D 11
38 V D D
* S C LK 12
37 S D A TA *
C LK _IN T 13
36 N /C
N /C 14
35 FB _IN T
V D D 15
34 V D D
A V D D 16
33 FB _O U TT
A G N D 17
32 N C
G N D 18
31 G N D
C LK C 3 19
30 C LK C 8
C LK T3 20
29 C LK T8
V D D 21
28 V D D
C LK T4 22
27 C LK T9
C LK C 4 23
26 C LK C 9
G N D 24
25 G N D
*: Internal pull-up resistor 120K to VDD
W83176R-735
- 2 -
4. BLOCK DIAGRAM
5. PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
*- Internal 120K
pull-up
W83176R-735
Publication Release Date: April 13, 2005
- 3 -
Revision 1.1
5.1 Clock Outputs
SYMBOL
PIN
I/O
FUNCTION
CLKC[9:0]
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
OUT
Complementory Clocks of differential pair outputs
CLKT[9:0]
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
OUT
True Clocks of differential pair outputs
SDATA *
37
I/O
Serial data of I
2
C 2-wire control interface
Internal pull-up resistor 120K to Vdd
SCLK *
12
IN
Serial clock of I
2
C 2-wire control interface
Internal pull-up resistor 120K to Vdd
CLK_INT
13
IN
True reference clock input, 3.3V tolerant input
NC
14, 32, 36
NONE
Not connected
FB_OUTT 33 OUT
True Feedback output, dedicated for external feedback.
It switches at the same frequency as the CLK. This
output must be wired to FB_INT.
FB_INT 35 IN
True Feedback input, provides feedback signal to the
internal PLL for synchronization with CLK_INT to
eliminate phase error.
5.2
Power Pins
SYMBOL
PIN
FUNCTION
GND
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
Ground
V
DD
4, 11, 15, 21, 28,
34, 38, 45
Power Supply 2.5V
AVDD
16
Analog power supply, 2.5V
AGND
17
Analog ground
W83176R-735
- 4 -
6. REGISTER 0 ~ REGISTER 4 RESERVED
6.1
Register 5: Output Control
(1 = Active, 0 = Inactive) (Default = FFH)
BIT
@POWERUP
PIN
DESCRIPTION
7
1
2, 3
CLKC0, CLKT0 output control
6
1
6, 5
CLKC1, CLKT1 output control
5
1
9, 10
CLKC2, CLKT2 output control
4
1
19, 20
CLKC3, CLKT3 output control
3
1
23, 22
CLKC4, CLKT4 output control
2
1
26, 27
CLKC9, CLKT9 output control
1 1 -
Reserved
0 1 -
Reserved
6.2
Register 6: Output Control
(1 = Active, 0 = Inactive) (Default = FFH)
BIT
@POWERUP
PIN
DESCRIPTION
7 1 -
Reserved
6 1 -
Reserved
5 1 -
Reserved
4
1
30, 29
CLKC8, CLKT8 output control
3
1
40, 39
CLKC7, CLKT7 output control
2
1
43, 44
CLKC6, CLKT6 output control
1
1
47, 46
CLKC5, CLKT5 output control
0 1 -
Reserved
W83176R-735
Publication Release Date: April 13, 2005
- 5 -
Revision 1.1
7. ACCESS INTERFACE
The W83176R-735 provides I
2
C Serial Bus for microprocessor to read/write internal registers. In the
W83176R-735 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I
2
C write
address is defined at 0xD4. The I
2
C read address is defined at 0xD5.
Block Read and Block Write Protocol
7.1 Block Write Protocol
7.2 Block Read Protocol
## In block mode, the command code must filled 00H
7.3 Byte Write Protocol
7.4 Byte Read Protocol
W83176R-735
- 6 -
8. SPECIFICATIONS
8.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs
must always be tied to an appropriate logic voltage level (Ground or VDD).
SYMBOL
PARAMETER
RATING
V
DD
, AVDD
Voltage on any pin with respect to GND
-0.5V to +3.6V
T
STG
Storage Temperature
-65
C to +150
C
T
B
Ambient Temperature
-55
C to +125
C
T
A
Operating Temperature
0
C to +70
C
8.2 A.C. Characteristics
VDD = AVDD = 2.5V
5 %, TA = 0
C to +70
C, Test load = 10 pF
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
Operating Clock
Frequency
FIN 100 200 MHz
Input Clock Duty Cycle
Dtin
40
60
%
Dynamic Supply Current
Idd
300
mA
Fin =100 to 200 MHz
Cycle to Cycle Jitter
C-
Cjitter
200
pS
Fout =100 to 200 MHz
Output to Output Skew
Tskew
100
pS
Fout =100 to 200 MHz
Output Clock Rise Time
Tor
650
950
pS
Fout =100 to 200 MHz
Output Clock Fall Time
Tof
650
950
pS
Fout =100 to 200 MHz
Output Clock Duty Cycle
Dtot
45
55
%
Fout =100 to 200 MHz
Output Differential-pair
Crossing Voltage
Voc
(VDD/2)
-0.2
VDD/
2
(VDD/2)
+ 0.2
V
Fout =100 to 200 MHz
8.3 D.C. Characteristics
VDD = AVDD = 2.5V
5%, TA = 0
C to +70
C
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
SDATA, SCLK Input Low Voltage
SV
IL
1.0
Vdc
SDATA, SCLK Input High Voltage
SV
IH
2.2 V
dc
CLKIN, FBIN Input Voltage Low
V
IL
0.4
V
dc
Fin = 100 to 200 MHz
CLKIN, FBIN Input Voltage High
V
IH
2.1 V
dc
Fin = 100 to 200 MHz
Input Pin Capacitance
C
IN
5 pF
Output Pin Capacitance
C
OUT
6 pF
Input Pin Inductance
L
IN
7 nH
9. ORDERING INFORMATION
W83176R-735
Publication Release Date: April 13, 2005
- 7 -
Revision 1.1
PART NUMBER
PACKAGE TYPE
PRODUCTION FLOW
W83176R_735
48-pin SSOP
Commercial, 0
C to +70
C
10. HOW TO READ THE TOP MARKING
1st line: Winbond logo and the type number: W83176R-735
2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code 342 G B
342: packages made in '2003, week 42
G: assembly house ID; O means OSE, G means GR
B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
W83176R-735
28051234
342G
B
W83176R-735
- 8 -
11. PACKAGE DRAWING AND DIMENSIONS
W83176R-735
Publication Release Date: April 13, 2005
- 9 -
Revision 1.1
12. REVISION HISTORY
VERSION DATE
PAGE
DESCRIPTION
n.a.
All of the versions before 0.50 are for internal
use.
0.5 12/18/03 3.7
Correction IC version, add register default
value and correction some description and
default value
1.0 05/06/04
Update to web
1.1 04/13/2005
Add
disclaimer
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
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No. 4, Creation Rd. III,
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TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
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TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
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Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
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