TPS2204A
TPS2206A
TPS2210A
SLVS449A DECEMBER 2002 REVISED MAY 2003
PC CARD
POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
FEATURES
D
Fully Integrated V
CC
and V
PP
Switching for
Single-Slot or Dual-Slot PC Card
Interface
D
P
2
C
3-Lead Serial Interface Compatible With
CardBus
Controller
D
Meets PC Card Standard
D
RESET for System Initialization of PC Cards
D
12-V Supplies Can Be Disabled Except During
12-V Flash Programming
D
Short-Circuit and Thermal Protection
D
24-Pin HTSSOP (PWP), 30-Pin SSOP (DB),
and 32-Pin TSSOP (DAP) Packages
D
Compatible With 3.3-V, 5-V, and 12-V PC
Cards
D
Low r
DS(on)
(95-m
, 5-V V
CC
Switch; 85-m
3.3-V V
CC
Switch)
D
Single-Slot Switch: TPS2210A
Dual-Slot Switch: TPS2204A and TPS2206A
D
Break-Before-Make Switching
APPLICATIONS
D
Notebook and Desktop Computers
D
Set-Top Boxes
D
Personal Digital Assistants(PDAs)
D
Digital Cameras
D
Bar Code Scanners
DESCRIPTION
The TPS2204A and TPS2206A PC CardBus
power-interface switches provide an integrated
power-management solution for two PC Card
sockets.
The TPS2210A is a single-slot option for this family of
devices. These devices allow the controlled distribution of
3.3 V, 5 V, and 12 V to each card slot. The current-limiting
and thermal-protection features eliminate the need for
fuses. Current-limit reporting helps the user isolate a
system fault. The switch r
DS(on)
and current-limit values
are set for the peak and average current requirements
stated in the PC Card
specification, and are optimized for
cost.
The TPS2206A is pin and/or functionally compatible with
the TPS2206, TPS2216, TPS2216A, TPS2226,
TPS2226A, and TPS2228 with a few exceptions, as
shown in the Available Options table.
AVAILABLE OPTIONS OF THE TPS2206A PIN COMPATABLE SWITCHES
PART NUMBER
INDEPENDENT
PIN VARIATION
INPUT
PART NUMBER
INDEPENDENT
VPP SWITCHING
RESET
RESET
SHDN
MODE
STBY
INPUT
VOLTAGES
TPS2206
No
Yes
Yes
No
No
No
3.3 V, 5 V, 12 V
TPS2206A
No
Yes
No
Yes
No
No
3.3 V, 5 V, 12 V
TPS2216
Yes/No(1)
Yes
Yes
No
Yes
Yes
3.3 V, 5 V, 12 V
TPS2216A
Yes/No(1)
Yes
Yes
No
Yes
Yes
3.3 V, 5 V, 12 V
TPS2226
Yes
Yes
No
Yes
No
No
3.3 V, 5 V, 12 V
TPS2226A
Yes
Yes
No
Yes
No
No
3.3 V, 5 V, 12 V
TPS2228
Yes
Yes
No
Yes
No
No
1.8 V, 3.3 V, 5 V
(1) Selected by MODE pin.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
P2C is a trademark of Texas Instruments.
PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright
2002 2003, Texas Instruments Incorporated
TPS2204A
TPS2206A
TPS2210A
SLVS449A DECEMBER 2002 REVISED MAY 2003
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES
TA
PLASTIC SMALL OUTLINE
(DB)
POWERPAD
PLASTIC SMALL
OUTLINE (DAP32)
POWERPAD
PLASTIC SMALL
OUTLINE (PWP24)
40
C to 85
C
TPS2206ADB
TPS2206ADAP
TPS2204APWP
TPS2210APWP
(1) The DB, PWP, and DAP packages are available taped and reeled. Add R suffix to device type (e.g., TPS2206ADBR) for taped and reeled.
PACKAGE DISSIPATION RATINGS
PACKAGE(1)
TA
25
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
TA = 85
C
POWER RATING
DB (30)
821.46 mW
10.95 mW/
C
328.58 mW
164.29 mW
DAP (32)
3191.4 mW
42.55 mW/
C
1276.5 mW
638.29 mW
PWP (24)
2491.6 mW
33.22 mW/
C
996.67 mW
498.33 mW
(1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
VI(3.3V)
0.3 V to 5.5
V
Input voltage range for card power
VI(5V)
0.3 V to 5.5
V
In ut voltage range for card ower
VI(12V)
0.3 V to 14
V
Logic input/output voltage
0.3 V to 6
V
Output voltage
VO(xVCC)
0.3 V to 6
V
Output voltage
VO(xVPP)
0.3 V to 14
V
Continuous total power dissipation
See Dissipation Rating Table
Output current
IO(xVCC)
Internally Limited
Output current
IO(xVPP)
Internally Limited
Operating virtual junction temperature range, TJ
40
C to 100
C
Storage temperature range, TSTG
55
C to 150
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds)
260
C
OC sink current
10
mA
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PowerPAD is a trademark of Texas Instruments.
TPS2204A
TPS2206A
TPS2210A
SLVS449A DECEMBER 2002 REVISED MAY 2003
www.ti.com
3
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
I
t
lt
V
i
i d f
ll i
it
ti
5 V
d
VI(3.3V)(1)
3
3.6
Input voltage, VI(3.3V) is required for all circuit operations. 5 V and
12 V are only required for their respective functions
VI(5V)
3
5.5
V
12 V are only required for their respective functions.
VI(12V)
7
13.5
V
Output current I
IO(xVCC) at TJ = 100
C
1
A
Output current, IO
IO(xVPP) at TJ = 100
C
100
mA
Clock frequency, f(clock)
2.5
MHz
Data
200
P l
d
ti
t
Latch
250
Pulse duration, tw
Clock
100
ns
Reset
100
Data-to-clock hold time, th (see Figure 2)
100
ns
Data-to-clock setup time, tsu (see Figure 2)
100
ns
Latch delay time, td(latch) (see Figure 2)
100
ns
Clock delay time, td(clock) (see Figure 2)
250
ns
Operating virtual junction temperature, TJ (maximum to be calculated at worst case PD at 85
C ambient)
40
100
C
(1) It is understood that for VI(3.3V)< 3 V, voltages within the absolute maximum ratings applied to pin 5 V or pin 12 V will not damage the IC.
ELECTRICAL CHARACTERISTICS
TJ = 25
C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted)
POWER SWITCH
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
3 3V to xVCC (2)
IO = 750 mA each
85
110
3.3V to xVCC (2)
IO = 750 mA each, TJ = 100
C
110
140
m
5V to xVCC(2)
IO = 500 mA each
95
130
m
r
Static drain-
source on state
5V to xVCC(2)
IO = 500 mA each, TJ = 100
C
120
160
rDS(on)
source on-state
resistance
3 3V or 5V to xVPP(2)
IO = 50 mA each
0.8
1
resistance
3.3V or 5V to xVPP(2)
IO = 50 mA each, TJ = 100
C
1
1.3
12V to xVPP (2)
IO = 50 mA each
2
2.5
12V to xVPP (2)
IO = 50 mA each, TJ = 100
C
2.5
3.4
Output discharge
Discharge at xVCC
IO(disc) = 1 mA
0.5
0.7
1
k
Out ut discharge
resistance
Discharge at xVPP
IO(disc) = 1 mA
0.2
0.4
0.5
k
Limit (steady-state value),
output powered into a short
IOS(xVCC)
1
1.4
2
A
I
Short circuit output current
output powered into a short
circuit
IOS(xVPP)
120
200
300
mA
IOS
Short-circuit output current
Limit (steady-state value),
output powered into a short
IOS(xVCC)
1
1.4
2
A
output powered into a short
circuit, TJ = 100
C
IOS(xVPP)
120
200
300
mA
Thermal shutdown
Thermal trip point, TJ
Rising temperature
135
C
Thermal shutdown
temperature(2)
Hysteresis, TJ
10
C
Current limit response time (3)(4)
5V to xVCC = 5 V, with 100-m
short to GND
10
s
Current-limit response time (3)(4)
5V to xVPP = 5 V, with 100-m
short to GND
3
s
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
(2) TPS2204A and TPS2206A: two switches on. TPS2210A: one switch on.
(3) Specified by design; not tested in production.
(4) From application of short to 110% of final current limit.
TPS2204A
TPS2206A
TPS2210A
SLVS449A DECEMBER 2002 REVISED MAY 2003
www.ti.com
4
ELECTRICAL CHARACTERISTICS Continued
TJ = 25
C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
N
l
II(3.3V)
V ( VCC)
V ( VPP)
3 3 V
d
140
200
Normal
operation
II(5V)
VO(xVCC) = VO(xVPP) = 3.3 V and
also for RESET = 0 V
8
12
I
Input current,
operation
II(12V)
also for RESET = 0 V
100
180
A
II
In ut current,
quiescent
Sh td
II(3.3V)
0.3
2
A
Shutdown
mode
II(5V)
VO(xVCC) = VO(xVPP) = Hi-Z
0.1
2
mode
II(12V)
VO(xVCC) VO(xVPP) Hi Z
0.3
2
VO(xVCC) = 5 V,
10
I
Leakage current,
Shutdown mode
VO(xVCC) = 5 V,
VI(5V) = VI(12V) = 0 V
TJ = 100
C
50
A
Ilkg
Leakage current,
output off state
Shutdown mode
VO(xVPP) = 12 V,
10
A
VO(xVPP) = 12 V,
VI(5V) = VI(12V) = 0 V
TJ = 100
C
50
LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
(1)
RESET = 5.5 V
1
1
II(RESET)(1)
RESET = 0 V
30
20
10
I (S
)
(1)
SHDN = 5.5 V
1
1
II
Input current, logic
II(SHDN)(1)
SHDN = 0 V
50
3
A
II
In ut current, logic
I
(1)
LATCH = 5.5 V
50
A
II(LATCH)(1)
LATCH = 0 V
1
1
II(CLOCK, DATA)
0 V to 5.5 V
1
1
VIH
High-level input voltage, logic
2
V
VIL
Low-level input voltage, logic
0.8
V
VO(sat)
Output saturation voltage at OC
IO = 2 mA
0.14
0.4
V
Ilkg
Leakage current at OC
VO(/OC) = 5.5 V
0
1
A
(1) LATCH has low current pulldown. RESET and SHDN have low-current pullup.
UVLO AND POR (POWER-ON RESET)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI(3.3V)
Input voltage at 3.3V pin, UVLO
3.3-V level below which all switches are Hi-Z
2.4
2.7
2.9
V
Vhys(3.3V)
UVLO hysteresis voltage at VA (1)
100
mV
VI(5V)
Input voltage at 5V pin, UVLO
5-V level below which only 5V switches are Hi-Z
2.3
2.5
2.9
V
Vhys(5V)
UVLO hysteresis voltage at 5 V(1)
100
mV
tdf
Delay time for falling response, UVLO(1)
Delay from voltage hit (step from 3 V to 2.3 V)
to Hi-Z control (90% VG to GND)
4
s
VI(POR)
Input voltage, power-on reset(1)
3.3-V voltage below which POR is asserted
causing a RESET internally with all line
switches open and all discharge switches
closed.
1.7
V
(1) Specified by design; not tested in production.
TPS2204A
TPS2206A
TPS2210A
SLVS449A DECEMBER 2002 REVISED MAY 2003
www.ti.com
5
SWITCHING CHARACTERISTICS
VCC = 5 V, TA = 25
C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V (not applicable for TPS2223A) all outputs unloaded (unless otherwise noted)
PARAMETER(1)
LOAD CONDITION
TEST CONDITIONS(2)
MIN
TYP
MAX
UNIT
CL(xVCC)= 0.1
F, CL(xVPP)= 0.1
F,
VO(xVCC) = 5 V
0.9
t
Output rise times(3)
CL(xVCC)= 0.1
F, CL(xVPP)= 0.1
F,
IO(xVCC) = 0 A, IO(xVPP) = 0 A
VO(xVPP) = 12 V
0.26
ms
tr
Output rise times(3)
CL(xVCC)= 150
F, CL(xVPP)= 10
F,
VO(xVCC) = 5 V
1.1
ms
CL(xVCC)= 150
F, CL(xVPP)= 10
F,
IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA VO(xVPP) = 12 V
0.6
CL(xVCC)= 0.1
F, CL(xVPP)= 0.1
F,
VO(xVCC) = 5 V,
Discharge switches ON
0.5
tf
Output fall times(3)
CL(xVCC)= 0.1
F, CL(xVPP)= 0.1
F,
IO(xVCC) = 0 A, IO(xVPP) = 0 A
VO(xVPP) = 12 V,
Discharge switches ON
0.2
ms
CL(xVCC)= 150
F, CL(xVPP)= 10
F,
VO(xVCC) = 5 V
2.35
CL(xVCC)= 150
F, CL(xVPP)= 10
F,
IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA VO(xVPP) = 12 V
3.9
Latch
to xVPP (12 V)
tpdon
2
Latch
to xVPP (12 V)
tpdoff
0.62
Latch
to xVPP (5 V)
tpdon
0.77
Latch
to xVPP (5 V)
tpdoff
0.51
CL(xVCC)= 0.1
F, CL(xVPP)= 0.1
F,
Latch
to xVPP (3 3 V)
tpdon
0.75
ms
CL(xVCC)= 0.1
F, CL(xVPP)= 0.1
F,
IO(xVCC) = 0 A, IO(xVPP) = 0 A
Latch
to xVPP (3.3 V)
tpdoff
0.52
ms
O(xVCC)
O(xVPP)
Latch
to xVCC (5 V)
tpdon
0.3
Latch
to xVCC (5 V)
tpdoff
2.5
Latch
to xVCC (3 3V)
tpdon
0.3
t
Propagation delay
Latch
to xVCC (3.3V)
tpdoff
2.8
tpd
Pro agation delay
times(3)
Latch
to xVPP (12 V)
tpdon
2.2
Latch
to xVPP (12 V)
tpdoff
0.8
Latch
to xVPP (5 V)
tpdon
0.8
Latch
to xVPP (5 V)
tpdoff
0.6
CL(xVCC)= 150
F, CL(xVPP)= 10
F,
Latch
to xVPP (3 3 V)
tpdon
0.8
ms
CL(xVCC)= 150
F, CL(xVPP)= 10
F,
IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA
Latch
to xVPP (3.3 V)
tpdoff
0.6
ms
O(xVCC)
O(xVPP)
Latch
to xVCC (5 V)
tpdon
0.6
Latch
to xVCC (5 V)
tpdoff
2.5
Latch
to xVCC (3 3V)
tpdon
0.5
Latch
to xVCC (3.3V)
tpdoff
2.6
(1) Refer to Parameter Measurement Information in Figure 1.
(2) No card inserted, assumes a 0.1-
F output capacitor (see Figure 1).
(3) Specified by design; not tested in production.
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