TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Low r
DS(on)
. . . 5
D
Avalanche Energy . . . 30 mJ
D
Eight Power DMOS-Transistor Outputs of
150-mA Continuous Current
D
500-mA Typical Current-Limiting Capability
D
Output Clamp Voltage . . . 50 V
D
Enhanced Cascading for Multiple Stages
D
All Registers Cleared With Single Input
D
Low Power Consumption
description
The TPIC6B596 is a monolithic, high-voltage,
medium-current power 8-bit shift register
designed for use in systems that require relatively
high load power. The device contains a built-in
voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other medium-
current or high-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the
shift-register clock (SRCK) and the register clock
(RCK), respectively. The storage register
transfers data to the output buffer when shift-
register clear (SRCLR) is high. When SRCLR is
low, all registers in the device are cleared. When
output enable (G) is held high, all data in the
output buffers is held low and all drain outputs are
off. When G is held low, data from the storage
register is transparent to the output buffers. When
data in the output buffers is low, the DMOS-
transistor outputs are off. When data is high, the
DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device
on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved
performance for applications where clock signals may be skewed, devices are not located near one another,
or the system must tolerate electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-
current capability. Each output provides a 500-mA typical current limit at T
C
= 25
C. The current limit decreases
as the junction temperature increases for additional device protection.
The TPIC6B596 is characterized for operation over the operating case temperature range of 40
C to 125
C.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
V
CC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
SRCLR
G
GND
NC
GND
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
SRCK
RCK
GND
DW OR N PACKAGE
(TOP VIEW)
logic symbol
2
SRG8
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
9
12
8
13
3
EN3
C2
R
C1
1D
G
RCK
SRCLR
SRCK
SER IN
4
6
5
14
7
16
15
18
17
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
NC No internal connection
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
G
RCK
SRCLR
SRCK
SER IN
CLR
D
C1
D
C2
CLR
D
C1
SER OUT
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
4
DRAIN0
5
DRAIN1
10, 11, 19
GND
6
DRAIN2
7
DRAIN3
14
DRAIN4
15
DRAIN5
16
DRAIN6
17
DRAIN7
9
8
3
12
13
18
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
D
C1
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
VCC
Input
GND
GND
DRAIN
50 V
20 V
25 V
12 V
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)
Logic supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, V
I
0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, V
DS
(see Note 2)
50 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode anode current
500 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-to-drain diode anode current (see Note 3)
1 A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
D
,
T
C
= 25
C (see Note 3)
500 mA
. . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, I
D
,
T
C
= 25
C 150
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, I
DM
,T
C
= 25
C (see Note 3)
500 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, E
AS
(see Figure 4)
30
mJ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, I
AS
(see Note 4)
500
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
40
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
40
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration
100
s and duty cycle
2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25
C, L = 200 mH, IAS = 0.5 A (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE
TC
25
C
POWER RATING
DERATING FACTOR
ABOVE TC = 25
C
TC = 125
C
POWER RATING
DW
1389 mW
11.1 mW/
C
278 mW
N
1050 mW
10.5 mW/
C
263 mW
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
MAX
UNIT
Logic supply voltage, VCC
4.5
5.5
V
High-level input voltage, VIH
0.85 VCC
V
Low-level input voltage, VIL
0.15 VCC
V
Pulsed drain output current, TC = 25
C, VCC = 5 V (see Notes 3 and 5)
500
500
mA
Setup time, SER IN high before SRCK
, tsu (see Figure 2)
15
ns
Hold time, SER IN high after SRCK
, th (see Figure 2)
15
ns
Pulse duration, tw (see Figure 2)
40
ns
Operating case temperature, TC
40
125
C
NOTES:
3. Pulse duration
100
s and duty cycle
2%.
5. Technique should limit TJ TC to 10
C maximum.
electrical characteristics, V
CC
= 5 V, T
C
= 25
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(BR)DSX Drain-to-source breakdown voltage
ID = 1 mA
50
V
VSD
Source-to-drain diode forward
voltage
IF = 100 mA
0.85
1
V
VOH
High-level output voltage,
IOH = 20
A, VCC = 4.5 V
4.4
4.49
V
VOH
g
g ,
SER OUT
IOH = 4 mA, VCC = 4.5 V
4
4.2
V
VOL
Low-level output voltage,
IOL = 20
A,
VCC = 4.5 V
0.005
0.1
V
VOL
g ,
SER OUT
IOL = 4 mA,
VCC = 4.5 V
0.3
0.5
V
IIH
High-level input current
VCC = 5.5 V,
VI = VCC
1
A
IIL
Low-level input current
VCC = 5.5 V,
VI = 0
1
A
ICC
Logic supply current
VCC = 5 5 V
All outputs off
20
100
A
ICC
Logic supply current
VCC = 5.5 V
All outputs on
150
300
A
ICC(FRQ)
Logic supply current at frequency
fSRCK = 5 MHz, CL = 30 pF,
All outputs off, See Figures 2 and 6
0.4
5
mA
IN
Nominal current
VDS(on) = 0.5 V,
IN = ID,
TC = 85
C
See Notes 5, 6, and 7
90
mA
IDSX
Off state drain current
VDS = 40 V,
VCC = 5.5 V
0.1
5
A
IDSX
Off-state drain current
VDS = 40 V,
VCC = 5.5 V, TC = 125
C
0.15
8
A
ID = 100 mA,
VCC = 4.5 V
4.2
5.7
rDS(on)
Static drain-source on-state
resistance
ID = 100 mA,
TC = 125
C,
VCC = 4.5 V
See Notes 5 and 6
and Figures 7 and 8
6.8
9.5
ID = 350 mA,
VCC = 4.5 V
5.5
8
NOTES:
5. Technique should limit TJ TC to 10
C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85
C.
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics, V
CC
= 5 V, T
C
= 25
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output from G
150
ns
tPHL
Propagation delay time, high-to-low-level output from G
CL = 30 pF,
ID = 100 mA,
90
ns
tr
Rise time, drain output
L
,
D
,
See Figures 1, 2, and 9
200
ns
tf
Fall time, drain output
200
ns
tpd
Propagation delay time, SRCK
to SEROUT
CL = 30 pF,
ID = 100 mA,
See Figure 2
15
ns
f(SRCK)
Serial clock frequency
CL = 30 pF,
ID = 100 mA,
See Note 8
10
MHz
ta
Reverse-recovery-current rise time
IF = 100 mA,
di/dt = 20 A/
s,
100
ns
trr
Reverse-recovery time
F
,
,
See Notes 5 and 6 and Figure 3
300
ns
NOTES:
5. Technique should limit TJ TC to 10
C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK
SEROUT propagation delay and setup time plus some timing margin.
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
R
JA
Thermal resistance junction to ambient
DW package
All 8 outputs with equal power
90
C/W
R
JA
Thermal resistance, junction-to-ambient
N package
All 8 outputs with equal power
95
C/W
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V
VCC
DRAIN
GND
SRCLR
SER IN
RL = 235
CL = 30 pF
(see Note B)
VOLTAGE WAVEFORMS
G
Output
SRCK
RCK
Word
Generator
(see Note A)
7
6
5
4
3
2
1
0
5 V
SRCK
5 V
G
5 V
SER IN
RCK
SRCLR
5 V
5 V
DUT
24 V
DRAIN1
24 V
0 V
0 V
0 V
0.5 V
0 V
10, 11, 19
8
13
3
12
9
0 V
4 7,
14 17
ID
2
NOTES: A. The word generator has the following characteristics: tr
10 ns, tf
10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50
.
B. CL includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
PDF 
ZIP