TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C NOVEMBER 1983 REVISED SEPTEMBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Microprocessor Peripheral or Standalone
Operation
D
8-Bit Resolution A/D Converter
D
Differential Reference Input Voltages
D
Conversion Time . . . 17
s Max
D
Total Access and Conversion Cycles Per
Second
TLC548 . . . up to 45 500
TLC549 . . . up to 40 000
D
On-Chip Software-Controllable
Sample-and-Hold Function
D
Total Unadjusted Error . . .
0.5 LSB Max
D
4-MHz Typical Internal System Clock
D
Wide Supply Range . . . 3 V to 6 V
D
Low Power Consumption . . . 15 mW Max
D
Ideal for Cost-Effective, High-Performance
Applications including Battery-Operated
Portable Instrumentation
D
Pinout and Control Signals Compatible
With the TLC540 and TLC545 8-Bit A/D
Converters and with the TLC1540 10-Bit
A/D Converter
D
CMOS Technology
description
The TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bit
switched-capacitor successive-approximation ADC. These devices are designed for serial interface with a
microprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use
only the input/output clock (I/O CLOCK) input along with the chip select (CS) input for data control. The
maximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of the
TLC549 is specified up to 1.1 MHz.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
0
C to 70
C
TLC548CD
TLC549CD
TLC548CP
TLC549CP
40
C to 85
C
TLC548ID
TLC549ID
TLC548IP
TLC549IP
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
REF +
ANALOG IN
REF
GND
V
CC
I/O CLOCK
DATA OUT
CS
D OR P PACKAGE
(TOP VIEW)
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C NOVEMBER 1983 REVISED SEPTEMBER 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541
devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHz
and requires no external components. The on-chip system clock allows internal device operation to proceed
independently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desired
for a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clock
allow high-speed data transfer and conversion rates of 45 500 conversions per second for the TLC548, and
40 000 conversions per second for the TLC549.
Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit that
can operate automatically or under microprocessor control, and a high-speed converter with differential
high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation from
logic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuit
allows conversion with a maximum total error of
0.5 least significant bit (LSB) in less than 17
s.
The TLC548C and TLC549C are characterized for operation from 0
C to 70
C. The TLC548I and TLC549I are
characterized for operation from 40
C to 85
C.
functional block diagram
REF
6
4
8
8
DATA
OUT
8-Bit
Analog-to
Digital
Converter
(Switched-
Capacitors)
8-to-1 Data
Selector
and
Driver
Output
Data
Regiser
Internal
System
Clock
Sample
and
Hold
7
5
2
3
1
ANALOG IN
REF +
CS
I/O CLOCK
Control
Logic and
Output Counter
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 k
TYP
Ci = 60 pF TYP
(equivalent input
capacitance)
5 M
TYP
ANALOG IN
ANALOG IN
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C NOVEMBER 1983 REVISED SEPTEMBER 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating sequence
ten
ten
tsu(CS)
B7
B0
B1
B2
B3
B4
B5
B6
B7
Conversion Data B
MSB
MSB
LSB
Hi-Z State
MSB
LSB
(see Note B)
MSB
Previous Conversion Data A
A7
A7
A6 A5 A4 A3 A2 A1 A0
Hi-Z State
Don't
1
1
(see Note A)
tconv
tsu(CS)
Access
Cycle B
8
8
7
6
5
4
3
2
7
6
5
4
3
2
CLOCK
I/O
CS
OUT
DATA
Care
Sample
Cycle B
Access
Cycle C
Sample
Cycle C
twH(CS)
NOTES: A. The conversion cycle, which requires 36 internal system clock periods (17
s maximum), is initiated with the eighth I/O clock pulse
trailing edge after CS goes low for the channel whose address exists in memory at the time.
B. The most significant bit (A7) is automatically placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6A0)
are clocked out on the first seven I/O clock falling edges. B7B0 follows in the same manner.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range at any input
0.3 V to V
CC
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range
0.3 V to V
CC
+
0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current range (any input)
10 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current range (all inputs)
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
(see Note 2): TLC548C, TLC549C
0
C to 70
C
. . . . . . . . . . . . .
TLC548I, TLC549I
40
C to 85
C
. . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTES:
1. All voltage values are with respect to the network ground terminal with the REF and GND terminals connected together, unless
otherwise noted.
2. The D package is not recommended below 40
C.
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C NOVEMBER 1983 REVISED SEPTEMBER 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
TLC548
TLC549
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
5
6
3
5
6
V
Positive reference voltage, Vref+ (see Note 3)
2.5
VCC VCC+0.1
2.5
VCC VCC+0.1
V
Negative reference voltage, Vref (see Note 3)
0.1
0
2.5
0.1
0
2.5
V
Differential reference voltage, Vref+, Vref (see Note 3)
1
VCC VCC+0.2
1
VCC VCC+0.2
V
Analog input voltage (see Note 3)
0
VCC
0
VCC
V
High-level control input voltage, VIH (for VCC = 4.75 V to 5.5 V)
2
2
V
Low-level control input voltage, VIL (for VCC = 4.75 V to 5.5 V)
0.8
0.8
V
Input/output clock frequency, fclock(I/O) (for VCC = 4.75 V to 5.5 V)
0
2.048
0
1.1
MHz
Input/output clock high, twH(I/O) (for VCC = 4.75 V to 5.5 V)
200
404
ns
Input/output clock low, twL(I/O) (for VCC = 4.75 V to 5.5 V)
200
404
ns
Input/output clock transition time, tt(I/O)
(for VCC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)
100
100
ns
Duration of CS input high state during conversion, twH(CS)
(for VCC = 4.75 V to 5.5 V) (see Operating Sequence)
17
17
s
Setup time, CS low before first I/O CLOCK, tsu(CS)
(for VCC = 4.75 V to 5.5 V) (see Note 5)
1.4
1.4
s
TLC548C, TLC549C
0
70
0
70
C
TLC548I, TLC549I
40
85
40
85
C
NOTES:
3. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied
to REF convert to all zeros (00000000). For proper operation, the positive reference voltage Vref+, must be at least 1 V greater than
the negative reference voltage, Vref. In addition, unadjusted errors may increase as the differential reference voltage, Vref+ Vref ,
falls below 4.75 V.
4. This is the time required for the I/O CLOCK input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2
s for remote data acquisition
applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.
5. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internal
system clock after CS
before responding to control input signals. This CS setup time is given by the ten and tsu(CS) specifications.
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C NOVEMBER 1983 REVISED SEPTEMBER 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 4.75 V to 5.5 V, f
clock(I/O)
= 2.048 MHz for TLC548 or 1.1 MHz for TLC549
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
VCC = 4.75 V, IOH = 360
A
2.4
V
VOL
Low-level output voltage
VCC = 4.75 V, IOL = 3.2 mA
0.4
V
IOZ
High impedance off state output current
VO = VCC,
CS at VCC
10
A
IOZ
High-impedance off-state output current
VO = 0,
CS at VCC
10
A
IIH
High-level input current, control inputs
VI = VCC
0.005
2.5
A
IIL
Low-level input current, control inputs
VI = 0
0.005
2.5
A
II( )
Analog channel on-state input current during sample
Analog input at VCC
0.4
1
A
II(on)
g
g
cycle
Analog input at 0 V
0.4
1
A
ICC
Operating supply current
CS at 0 V
1.8
2.5
mA
ICC + Iref
Supply and reference current
Vref+ = VCC
1.9
3
mA
Ci
Input capacitance
Analog inputs
7
55
pF
Ci
Input capacitance
Control inputs
5
15
pF
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 4.75 V to 5.5 V, f
clock(I/O)
= 2.048 MHz for TLC548 or 1.1 MHz for TLC549
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC548
TLC549
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
EL
Linearity error
See Note 6
0.5
0.5
LSB
EZS
Zero-scale error
See Note 7
0.5
0.5
LSB
EFS
Full-scale error
See Note 7
0.5
0.5
LSB
Total unadjusted error
See Note 8
0.5
0.5
LSB
tconv
Conversion time
See Operating Sequence
8
17
12
17
s
Total access and conversion time
See Operating Sequence
12
22
19
25
s
ta
Channel acquisition time (sample cycle)
See Operating Sequence
4
4
I/O
clock
cycles
tv
Time output data remains
valid after I/O CLOCK
10
10
ns
td
Delay time to data output valid
I/O CLOCK
200
400
ns
ten
Output enable time
1.4
1.4
s
tdis
Output disable time
150
150
ns
tr(bus)
Data bus rise time
See Figure 1
300
300
ns
tf(bus)
Data bus fall time
300
300
ns
All typicals are at VCC = 5 V, TA = 25
C.
NOTES:
6. Linearity error is the deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
8. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
PDF 
ZIP