SN75LVDS84A
FLATLINK
TM
TRANSMITTER
SLLS354C MAY 1999 REVISED NOVEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
21:3 Data Channel Compression at up to
196 Million Bytes per Second Throughput
D
Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
D
21 Data Channels Plus Clock In
Low-Voltage TTL inputs and 3 Data
Channels Plus Clock Out Low-Voltage
Differential Signaling (LVDS) Outputs
D
Operates From a Single 3.3-V Supply and
89 mW (Typ)
D
Ultra Low Power 3.3-V CMOS Version of the
SN75LVDS84. Power Consumption About
One Third of the 'LVDS84
D
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20 Mil Terminal
Pitch
D
Consumes Less Than 0.54 mW When
Disabled
D
Wide Phase-Lock Input Frequency Range:
31 MHz to 75 MHz
D
No External Components Required for PLL
D
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA644 Standard
D
SSC Tracking Capability of 3% Center
Spread at 50-kHz Modulation Frequency
D
Improved Replacement for SN75LVDS84
and NSC's DS90CF363A 3-V Device
description
The SN75LVDS84A FlatLink transmitter contains three 7-bit parallel-load serial-out shift registers, and four
low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits
of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a
compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.
When transmitting, data bits D0 D20 are each loaded into registers of the 'LVDS84A upon the falling edge.
The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The
three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.
The 'LVDS84A requires no external components and little or no control. The data bus appears the same at the
input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only
user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut
off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers
to a low level.
The SN75LVDS84A is characterized for operation over ambient free-air temperatures of 0
_
C to 70
_
C.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
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2
3
4
5
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D4
V
CC
D5
D6
GND
D7
D8
V
CC
D9
D10
GND
D11
D12
NC
D13
D14
GND
D15
D16
D17
V
CC
D18
D19
GND
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV
CC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKIN
D20
DGG PACKAGE
(TOP VIEW)
NC Not Connected
SN75LVDS84A
FLATLINK
TM
TRANSMITTER
SLLS354C MAY 1999 REVISED NOVEMBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
Control Logic
CLK
CLKINH
PLL
SHTDN
CLKIN
D14 D20
D7 D13
D0 D6
Y0P
Y0M
Y1P
Y1M
Y2P
Y2M
CLKOUTP
CLKOUTM
schematics of input and output
VCC
180
5 V
D or
SHTDN
VCC
7 V
YnP or YnM
EQUIVALENT OF EACH INPUT
EQUIVALENT OF EACH OUTPUT
7 V
SN75LVDS84A
FLATLINK
TM
TRANSMITTER
SLLS354C MAY 1999 REVISED NOVEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and output voltage ranges, V
I
, V
O
(all terminals)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: ESD machine model
200 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD human-body model
6000 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD charged-device model
1500 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
_
C to 150
_
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
_
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
DGG
1316 mW
13.1 mW/
C
726 mW
This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH
2
V
Low-level input voltage, VIL
0.8
V
Differential load impedance, ZL
90
132
Operating free-air temperature, TA
0
70
C
timing requirements
MIN
NOM
MAX
UNIT
tc
Input clock period
13.3
tc
32.4
ns
tw
Pulse duration, high-level input clock
0.4 tc
0.6 tc
ns
tt
Transition time, input signal
5
ns
tsu
Setup time, data, D0 D20 valid before CLKIN
(See Figure 2)
3
ns
th
Hold time, data, D0 D20 valid after CLKIN
(See Figure 2)
1.5
ns
SN75LVDS84A
FLATLINK
TM
TRANSMITTER
SLLS354C MAY 1999 REVISED NOVEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT
Input threshold voltage
1.4
V
|VOD|
Differential steady-state output voltage magni-
tude
RL = 100
,
See Figure 3
247
454
mV
|VOD|
Change in the steady-state differential output
voltage magnitude between opposite binary
states
50
mV
VOC(SS)
Steady-state common-mode output voltage
RL = 100
,
See Figure 3
1.125
1.375
V
VOC(PP)
Peak-to-peak common-mode output voltage
80
150
mV
IIH
High-level input current
VIH = VCC
20
A
IIL
Low-level input current
VIL = 0
10
A
IOS
Short circuit output current
VO(Yn) = 0
6
24
mA
IOS
Short-circuit output current
VOD = 0
6
12
mA
IOZ
High-impedance output current
VO = 0 to VCC
10
A
Disabled,
All inputs at GND
15
150
A
Enabled,
RL = 100
(4 places)
f = 65 MHz
27
35
ICC(AVG)
Quiescent supply current (average)
L
(
)
Gray-scale pattern
(see Figure 4)
f = 75 MHz
30
38
mA
Enabled,
RL = 100
, (4 places)
f = 65 MHz
28
36
mA
L
, (
)
Worst-case pattern
(see Figure 5)
f = 75 MHz
31
39
CI
Input capacitance
2
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
SN75LVDS84A
FLATLINK
TM
TRANSMITTER
SLLS354C MAY 1999 REVISED NOVEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td0
Delay time, CLKOUT
to serial bit
position 0
0.2
0.2
ns
td1
Delay time, CLKOUT
to serial bit
position 1
1
7
tc
*
0.2
1
7
tc
)
0.2
ns
td2
Delay time, CLKOUT
to serial bit
position 2
t
15 38
(
0 2%)
2
7
tc
*
0.2
2
7
tc
)
0.2
ns
td3
Delay time, CLKOUT
to serial bit
position 3
tc = 15.38 ns (
0.2%),
|Input clock jitter| < 50 ps,
See Figure 6
3
7
tc
*
0.2
3
7
tc
)
0.2
ns
td4
Delay time, CLKOUT
to serial bit
position 4
See Figure 6
4
7
tc
*
0.2
4
7
tc
)
0.2
ns
td5
Delay time, CLKOUT
to serial bit
position 5
5
7
tc
*
0.2
5
7
tc
)
0.2
ns
td6
Delay time, CLKOUT
to serial bit
position 6
6
7
tc
*
0.2
6
7
tc
)
0.2
ns
tsk(o)
Output skew, tn
*
n
7
tc
0.2
0.2
ns
td7
Delay time, CLKIN
to CLKOUT
tc = 15.38 ns (
0.2%),
|Input clock jitter| < 50 ps,
See Figure 6
2.7
ns
t ( ) C cle time o tp t clock jitter
tc = 15.38 + 0.308 sin (2
500E3t)
0.05 ns,
See Figure 7
62
ps
tc(o) Cycle time, output clock jitter
tc = 15.38 + 0.308 sin (2
3E6t)
0.05 ns,
See Figure 7
121
ps
tw
Pulse duration, high-level output clock
4
7
tc
ns
tt
Transition time, differential output
voltage (tr or tf)
See Figure 3
700
1500
ps
ten
Enable time, SHTDN
to phase lock
(Yn valid)
See Figure 8
1
ms
tdis
Disable time, SHTDN
to off state
(CLKOUT low)
See Figure 9
6.5
ns
All typical values are at VCC = 3.3 V, TA = 25
C.
|Input clock jitter| is the magnitude of the change in the input clock period.
Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles.
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