SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS006A D2611, OCTOBER 1985 REVISED FEBRUARY 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
8-Channel Bidirectional Transceivers
Power-Up/Power-Down Protection
(Glitch Free)
High-Speed Low-Power Schottky Circuitry
Low Power Dissipation . . . 66 mW Max Per
Channel
High-impedance PNP Inputs
Receiver Hysteresis . . . 650 mV Typ
Open-Collector Driver Output Option
No Loading of Bus When Device Is
Powered Down (V
CC
= 0)
description
The SN75163B octal general-purpose interface
bus transceiver is a monolithic, high-speed, low-
power Schottky device. It is designed for two-way
data communications over single-ended transmission lines. The transceiver features driver outputs that can be
operated in either the open-collector or 3-state modes. If talk enable (TE) is high, these outputs have the
characteristics of open-collector outputs when pullup enable (PE) is low and of 3-state outputs when PE is high.
Taking TE low places the outputs in the high-impedance state. The driver outputs are designed to handle loads
of up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and 400 mV
of hysteresis for increased noise immunity.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when V
CC
= 0.
The SN75163B is characterized for operation from 0
C to 70
C.
Function Tables
INPUTS
OUTPUT
D
L
H
X
EACH RECEIVER
B
TE
PE
L
L
H
X
X
X
L
H
Z
INPUTS
OUTPUT
B
H
L
H
L
X
EACH DRIVER
D
TE
PE
H
H
X
H
L
H
H
L
L
X
H
L
Z
L
Z
H = high level, L = low level, X = irrelevant, Z = high-impedance state
TE
B1
B2
B3
B4
B5
B6
B7
B8
GND
VCC
D1
D2
D3
D4
D5
D6
D7
D8
PE
DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GPIB
I/O Ports
Terminal
I/O Ports
NOT RECOMMENDED FOR NEW DESIGN
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS006A D2611, OCTOBER 1985 REVISED FEBRUARY 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
logic diagram (positive logic)
D8
12
M1 (3S)
M2 (0C)
EN3 (XMT)
EN4 (RCV)
9
D7
13
8
B8
D6
14
7
B7
D5
15
6
B6
D4
16
5
B5
D3
17
4
B4
D2
18
3
B3
2
B1
TE
1
PE
11
19
D1
4
1
3(1 /2
)
B2
Terminal
I/O Ports
GPIB
I/O
Ports
B8
9
D8
12
B7
8
D7
13
B6
7
D6
14
B5
6
D5
15
B4
5
D4
16
B3
4
D3
17
B2
3
D2
18
11
PE
1
TE
19
D1
2
B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates open-collector outputs
{
schematics of inputs and outputs
NOM
9 k
GND
Input
VCC
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
Driver output Req = 30
NOM
Receiver output Req = 110
NOM
NOM
4 k
Req
10 k
NOM
Input/Output Port
VCC
GND
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS006A D2611, OCTOBER 1985 REVISED FEBRUARY 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level driver output current
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Note 2)
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
DW
1125 mW
9.0 mW/
C
720 mW
N
1150 mW
9.2 mW/
C
736 mW
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.75
5
5.25
V
High-level input voltage, VIH
2
V
Low-level input voltage, VIL
0.8
V
High level output current IOH
Bus ports with pullups active
10
mA
High-level output current, IOH
Terminal ports
800
A
High level output current IOL
Bus ports
48
mA
High-level output current, IOL
Terminal ports
16
mA
Operating free-air temperature, TA
0
70
C
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS006A D2611, OCTOBER 1985 REVISED FEBRUARY 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Input clamp voltage
II = 18 mA
0.8
1.5
V
Vhys
Hysteresis (VT + VT )
Bus
See Figure 8
0.4
0.65
V
VOH
High level output voltage
Terminal
IOH = 800
A,
TE at 0.8 V
2.7
3.5
V
VOH
High-level output voltage
Bus
IOH = 10 mA,
PE and TE at 2 V
2.5
3.3
V
VOL
Low level output voltage
Terminal
IOL = 16 mA,
TE at 0.8 V
0.3
0.5
V
VOL
Low-level output voltage
Bus
IOL = 48 mA,
PE and TE at 2 V
0.4
0.5
V
IOH
High-level output current
Bus
VO = 5.5 V,
PE at 0.8 V,
100
A
IOH
g
(open-collector mode)
Bus
O
,
D and TE at 2 V
,
100
A
IOZ
Off-state output current
Bus
PE at 2 V,
VO = 2.7 V
20
A
IOZ
(3-state mode)
Bus
,
TE at 0.8 V
VO = 0.4 V
20
A
II
Input current at maximum
input voltage
Terminal
VI = 5.5 V
0.2
100
A
IIH
High-level input current
Terminal
VI = 2.7 V
0.1
20
A
IIL
Low-level input current
Terminal
VI = 0.5 V
10
100
A
IOS
Short circuit output current
Terminal
15
35
75
mA
IOS
Short-circuit output current
Bus
25
50
125
mA
IIL
Supply current
No load
Receivers low and enabled
80
mA
IIL
Supply current
No load
Drivers low and enabled
100
mA
CI/O(bus) Bus-port capacitance
VCC = 5 V to 0,
VI/O = 0 to 2 V, f = 1 MHz
30
pF
All typical values are at VCC = 5, TA = 25
C.
switching characteristics, V
CC
= 5 V, C
L
= 15 pF, T
A
= 25
C (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
Terminal
Bus
CL = 30 pF,
14
20
ns
tPHL
Propagation delay time, high-to-low-level output
Terminal
Bus
L
,
See Figure 1
14
20
ns
tPLH
Propagation delay time, low-to-high-level output
Bus
Terminal
CL = 30 pF,
10
20
ns
tPHL
Propagation delay time, high-to-low-level output
Bus
Terminal
L
,
See Figure 2
15
22
ns
tPZH
Output enable time to high level
25
35
tPHZ
Output disable time from high level
TE
Bus
See Figure 3
13
22
ns
tPZL
Output enable time to low level
TE
Bus
See Figure 3
22
35
ns
tPLZ
Output disable time from low level
22
32
tPZH
Output enable time to high level
20
30
tPHZ
Output disable time from high level
TE
Terminal
See Figure 4
12
20
ns
tPZL
Output enable time to low level
TE
Terminal
See Figure 4
23
32
ns
tPLZ
Output disable time from low level
19
30
ten
Output pullup enable time
PE
Terminal
See Figure 5
15
22
ns
tdis
Output pullup disable time
PE
Terminal
See Figure 5
13
20
ns
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS006A D2611, OCTOBER 1985 REVISED FEBRUARY 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
TEST CIRCUIT
tPHL
1.0 V
1.5 V
2.2 V
1.5 V
D Input
tPLH
B Output
3 V
0 V
VOH
VOH
B
3 V
TE
(see Note B)
CL = 30 pF
480
200
5 V
Output
50
D
3 V
PE
Generator
(see Note A)
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
TEST CIRCUIT
1.5 V
1.5 V
tPHL
1.5 V
1.5 V
B Input
tPLH
D Output
3 V
0 V
VOH
VOL
D
CL = 30 pF
(see Note B)
3 k
240
4.3 V
Output
TE
B
50
Generator
(see Note A)
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
480
CL = 15 pF
(see Note B)
TEST CIRCUIT
VOLTAGE WAVEFORMS
VOL
3.5 V
0.8 V
VOH
0 V
3 V
tPHZ
tPLZ
0.5 V
90%
1.5 V
1.0 V
2 V
1.5 V
TE Input
S2 Closed
S1 to GND
B Output
tPZL
S2 Open
tPZH
S1 to 3 V
B Output
TE
S2
3 V
S1
B
200
5 V
Output
PE
D
50
Generator
(see Note A)
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
1 MHz, 50% duty cycle, tr
6 ns, tf
6 ns,
ZO = 50
.
B. CL includes probe and jig capacitance.
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