SN54LV165A, SN74LV165A
PARALLEL LOAD 8 BIT SHIFT REGISTERS
SCLS402K - APRIL 1998 - REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2-V to 5.5-V V
CC
Operation
D
Max t
pd
of 10.5 ns at 5 V
D
Support Mixed-Mode Voltage Operation on
All Ports
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN54LV165A . . . J OR W PACKAGE
SN74LV165A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
D
C
NC
B
A
E
F
NC
G
H
SN54LV165A . . . FK PACKAGE
(TOP VIEW)
CLK
SH/LD
NC
SER
CLK INH
H
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
Q
H
GND
V
CC
CLK INH
D
C
B
A
SER
Q
H
Q
H
Q
NC - No internal connection
SN74LV165A . . . RGY PACKAGE
(TOP VIEW)
1
16
8
9
2
3
4
5
6
7
15
14
13
12
11
10
CLK INH
D
C
B
A
SER
CLK
E
F
G
H
Q
H
SH/LD
V
GND
CC
description/ordering information
The 'LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V V
CC
operation.
When the devices are clocked, data is shifted toward the serial output Q
H
. Parallel-in access to each stage is
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input.
The 'LV165A devices feature a clock-inhibit function and a complemented serial output, Q
H
.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN - RGY
Reel of 1000
SN74LV165ARGYR
LV165A
SOIC - D
Tube of 40
SN74LV165AD
LV165A
SOIC - D
Reel of 2500
SN74LV165ADR
LV165A
SOP - NS
Reel of 2000
SN74LV165ANSR
74LV165A
-40
C to 85
C
SSOP - DB
Reel of 2000
SN74LV165ADBR
LV165A
-40 C to 85 C
Tube of 90
SN74LV165APW
TSSOP - PW
Reel of 2000
SN74LV165APWR
LV165A
TSSOP - PW
Reel of 250
SN74LV165APWT
LV165A
TVSOP - DGV
Reel of 2000
SN74LV165ADGVR
LV165A
CDIP - J
Tube of 25
SNJ54LV165AJ
SNJ54LV165AJ
-55
C to 125
C
CFP - W
Tube of 150
SNJ54LV165AW
SNJ54LV165AW
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54LV165AFK
SNJ54LV165AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV165A, SN74LV165A
PARALLEL LOAD 8 BIT SHIFT REGISTERS
SCLS402K - APRIL 1998 - REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a
low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only
while CLK is high. Parallel loading is inhibited when SH/ LD is held high. The parallel inputs to the register are
enabled while SH/ LD is held low, independently of the levels of CLK, CLK INH, or SER.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OPERATION
SH/ LD
CLK
CLK INH
OPERATION
L
X
X
Parallel load
H
H
X
Q0
H
X
H
Q0
H
L
Shift
H
L
Shift
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
QH
QH
11
12
13
14
3
4
5
6
A
B
C
D
E
F
G
H
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
SN54LV165A, SN74LV165A
PARALLEL LOAD 8 BIT SHIFT REGISTERS
SCLS402K - APRIL 1998 - REVISED APRIL 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical shift, load, and inhibit sequences
Serial Shift
Inhibit
Load
E
QH
H
G
C
F
Data
Inputs
D
SH/LD
SER
CLK INH
CLK
B
A
QH
L
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
SN54LV165A, SN74LV165A
PARALLEL LOAD 8 BIT SHIFT REGISTERS
SCLS402K - APRIL 1998 - REVISED APRIL 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DB package
82
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package
120
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package
108
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package
39
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LV165A, SN74LV165A
PARALLEL LOAD 8 BIT SHIFT REGISTERS
SCLS402K - APRIL 1998 - REVISED APRIL 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54LV165A
SN74LV165A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
2
5.5
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC
0.7
VCC
0.7
V
VIH
High-level input voltage
VCC = 3 V to 3.6 V
VCC
0.7
VCC
0.7
V
VCC = 4.5 V to 5.5 V
VCC
0.7
VCC
0.7
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
VCC
0.3
VCC
0.3
V
VIL
Low-level input voltage
VCC = 3 V to 3.6 V
VCC
0.3
VCC
0.3
V
VCC = 4.5 V to 5.5 V
VCC
0.3
VCC
0.3
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
-50
-50
A
IOH
High-level output current
VCC = 2.3 V to 2.7 V
-2
-2
IOH
High-level output current
VCC = 3 V to 3.6 V
-6
-6
mA
VCC = 4.5 V to 5.5 V
-12
-12
mA
VCC = 2 V
50
50
A
IOL
Low-level output current
VCC = 2.3 V to 2.7 V
2
2
IOL
Low-level output current
VCC = 3 V to 3.6 V
6
6
mA
VCC = 4.5 V to 5.5 V
12
12
mA
VCC = 2.3 V to 2.7 V
200
200
t/
v
Input transition rise or fall rate
VCC = 3 V to 3.6 V
100
100
ns/V
t/
v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V
20
20
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SN54LV165A
SN74LV165A
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
IOH = -50
A
2 V to 5.5 V
VCC-0.1
VCC-0.1
VOH
IOH = -2 mA
2.3 V
2
2
V
VOH
IOH = -6 mA
3 V
2.48
2.48
V
IOH = -12 mA
4.5 V
3.8
3.8
IOL = 50
A
2 V to 5.5 V
0.1
0.1
VOL
IOL = 2 mA
2.3 V
0.4
0.4
V
VOL
IOL = 6 mA
3 V
0.44
0.44
V
IOL = 12 mA
4.5 V
0.55
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
20
20
A
Ioff
VI or VO = 0 to 5.5 V
0
5
5
A
Ci
VI = VCC or GND
3.3 V
1.7
1.7
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PDF 
ZIP