SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C JANUARY 2001 REVISED JANUARY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
UBT
Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, and Clock-Enabled Mode
D
TI-OPC
Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D
OEC
Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D
GTLP Buffered CLKAB Signal (CLKOUT)
D
LVTTL Interfaces Are 5-V Tolerant
D
Medium-Drive GTLP Outputs (50 mA)
D
LVTTL Outputs (24 mA/24 mA)
D
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D
Bus Hold on A-Port Data Inputs
D
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description
The SN74GTLPH16916 is a medium-drive, 17-bit UBT
transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes
of data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and conversion
of a GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC
circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 19
.
Copyright
2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.
DGG OR DGV PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
CLKIN
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
BIAS V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
CLKOUT
CLKBA
CEBA
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C JANUARY 2001 REVISED JANUARY 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH16916 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V
and V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40
C to 85
C
TSSOP DGG
Tape and reel
SN74GTLPH16916GR
GTLPH16916
40
C to 85
C
TVSOP DGV
Tape and reel
SN74GTLPH16916VR
GL916
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C JANUARY 2001 REVISED JANUARY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
The SN74GTLPH16916 is a medium-drive (50 mA), 17-bit UBT transceiver containing D-type latches and
D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can
replace any of the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH16916 UBT
Transceiver Replacement Functions
FUNCTION
8 BIT
9 BIT
10 BIT
16 BIT
18 BIT
Transceiver
'245, '623, '645
'863
'861
'16245, '16623
'16863
Buffer/driver
'241, '244, '541
'827
'16241, '16244, '16541
'16825
Latched transceiver
'543
'16543
'16472
Latch
'373, '573
'843
'841
'16373
'16843
Registered transceiver
'646, '652
'16646, '16652
'16474
Flip-flop
'374, '574
'821
'16374
Standard UBT
'16500, '16501
Universal bus driver
'16835
Registered transceiver with clock enable
'2952
'16470, '16952
Flip-flop with clock enable
'377
'823
'16823
Standard UBT with clock enable
'16600, '16601
SN74GTLPH16916 UBT transceiver replaces all above functions
Additionally, the SN74GTLPH16916 allows for transparent conversion of CLKAB-to-GTLP signal levels
(CLKOUT) and CLKOUT-to-LVTTL logic levels (CLKIN).
Data flow in each direction is controlled by clock enables (CEAB and CEBA), latch enables (LEAB and LEBA),
clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA enable all 17 bits, and
OEAB and OEBA control the 17 bits of data and the CLKOUT/CLKIN buffered clock path for the A-to-B and
B-to-A directions, respectively.
For A-to-B data flow when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data
is latched regardless of the state of CLKAB (high or low) and, if LEAB is high, the device is in transparent mode.
When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except CEBA, OEBA, LEBA, and CLKBA are used.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C JANUARY 2001 REVISED JANUARY 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Function Tables
OUTPUT ENABLE
INPUTS
OUTPUT
MODE
CEAB
OEAB
LEAB
CLKAB
A
B
MODE
X
H
X
X
X
Z
Isolation
L
L
L
H
X
B0
Latched storage of A data
L
L
L
L
X
B0
Latched storage of A data
X
L
H
X
L
L
True transparent
X
L
H
X
H
H
True transparent
L
L
L
L
L
Clocked storage of A data
L
L
L
H
H
Clocked storage of A data
H
L
L
X
X
B0
Clock inhibit
A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and
CLKBA. The condition when OEAB and OEBA are both low at the same time is not
recommended.
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
Output level before the indicated steady-state input conditions were established
BUFFERED CLOCK
INPUTS
OPERATION OR
MODE
CE
LE
OEAB
OEBA
FUNCTION
MODE
X
X
H
H
Z
Isolation
X
X
L
H
CLKAB to CLKOUT
True delayed clock signal
X
X
H
L
CLKOUT to CLKIN
True delayed clock signal
X
X
L
L
CLKAB to CLKOUT,
CLKOUT to CLKIN
True delayed clock signal
with feedback path
This condition is not recommended.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C JANUARY 2001 REVISED JANUARY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
1 of 17 Channels
CE
CE
CLKOUT
CLKIN
1
56
55
2
28
30
29
27
3
54
31
26
VREF
35
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