SN74ALS819, SN74ALS29818
8-BIT DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1986, Texas Instruments Incorporated
1
High-Speed 8-Bit Parallel Pipeline Register
Serial Shadow Register With Right-Shift Only
'ALS29818 Performs Parallel-to-Serial and
Serial-to-Parallel Conversion
Designed Specifically for Use in Applications
Such As:
Write Control Store ('ALS29818)
Serial Shadow-Register Diagnostics
'ALS819 Provides Even-Parity Output
Low Power Dissipation . . . 215 mW Typical
'ALS29818 is Functionally Equivalent to AMD
AM29818
Package Options include Plastic Small Outline
Packages, Standard Plastic DIPs, and Plastic
Chip Carriers
description
The SN74ALS819 and SN74ALS29818 are 8-bit
pipeline registers each with an on-chip shadow
register. They are for use in applications such as
write control store and shadow register diagnos-
tics.
The output registers of the 'ALS819 and
'ALS29818 are loaded in parallel from either the
I/O port (DQ0 DQ7) or the shadow register. The
shadow register of the 'ALS2981A 8 can be
loaded serially or from either the I/O port (Y0 Y7)
or the pipeline register. The 'ALS819 shadow
register can be loaded serially or from the I/O port
(DQ0 DQ7). In addition, the 'ALS819 provides a
Parity-Even (PE) output, which monitors parity of
the output register. Operation of these devices is
controlled by the Mode and SDI inputs as shown
in the function table.
The SN74ALS819 and SN74ALS29818 are
characterized for operation from 0
C to 70
C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
4
4 3
16 17
14
18
15
3
5
6
7
8
9
10
11
13
12
2
PE
SRCLK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SDI
GND
SN74ALS819 . . . DW OR JT PACKAGE
(TOP VIEW)
SN74ALS819 . . . FN PACKAGE
(TOP VIEW)
SN74ALS29818 . . . DW OR NT PACKAGE
(TOP VIEW)
SN74ALS29818 . . . FN PACKAGE
(TOP VIEW)
NC No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
MODE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SDO
ORCLK
1
Y1
Y2
Y3
NC
Y4
Y5
Y6
DQ1
DQ2
DQ3
NC
DQ4
DQ5
DQ6
SDI
GND
NC
ORCLK
SD0
Y7
DQ0
SRCLK
PE
NC
28 27 26
25
24
23
22
21
20
19
DQ7
MODE
Y0
CC
V
OEY
SRCLK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SDI
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
MODE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SDO
ORCLK
SDI
GND
NC
ORCLK
SD0
Y7
DQ0
SRCLK
OEY
NC
DQ7
MODE
Y0
CC
V
5
6
7
8
9
10
11
13
12
14
2 1
Y1
Y2
Y3
NC
Y4
Y5
Y6
DQ1
DQ2
DQ3
NC
DQ4
DQ5
DQ6
15 16 1718
28 27 26
25
24
23
22
21
20
19
SN74ALS819, SN74ALS29818
8-BIT DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
logic diagrams (positive logic)
Shadow
Y7Y0
15 22
2k
PE
1
8
8
1D
8 X
8
8
8
8
8 X
EN
Buffers
3-State
C1
Register
SD0
Pipeline
14
1
1
G1
MUX
SN74ALS819
13
ORCLK
Register
SRG8
M1
/C2
[0]
1
1,2D
1,2D
1,2D
SN74ALS29818
SDO
14
Buffer
3-State
15 22
Y7Y0
8
8
8 X
8
1D
8 X
EN
C1
Register
Pipeline
G1
8
8 X MUX
1
1
8
8
8
8
8
8 X
EN
Buffer
3-State
1
1
G1
MUX
1D
C1
[6]
[2]
[3]
[4]
[5]
[7]
23
2
MODE
SRCLK
11
SD1
SR7
8
8
8
10 3
DQ7DQ0
2
13
1
OEY
ORCLK
SRCLK
23
11
SD1
MODE
SRG8
M1
/C3
1
M2
[0]
1,3D
1,2,3D
[6]
1,2,3D [1]
[2]
[3]
[4]
[5]
[7]
8
SR7
10 3
8
DQ7DQ0
[1]
Shadow
Register
Pin numbers shown are for DW and NT packages.
SN74ALS819
8-BIT DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
SN74ALS819 gate-level logic diagram (positive logic)
21
QY1
Y1
QY1
Sheet
To Next
QY0
22
Y0
QY0
Sheet
To Next
D
C1
D
C1
D
C1
D
Y5
19
20
18
Y2
17
Y3
C1
Y4
Y6
16
Sheet
14
QY7
To Next
SDO
Sheet
To Next
QY7
Y7
15
D
C1
DQ6
9
DQ5
8
DQ4
7
DQ3
6
10
C1
DQ7
D
3
DQ0
4
DQ1
DQ2
5
Not Shown
5 Identical Sections
QY6
QY5
QY4
QY3
QY3
QY2
QY6
QY5
QY4
QY2
23
11
2
13
MODE
SDI
ORCLK
SRCLK
Pin numbers shown are for DW and NT packages.
SN74ALS819
8-BIT DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
SN74ALS819 gate-level logic diagram (positive logic) (continued)
Sheet
From Previous
QY0
QY1
QY2
QY3
QY3
QY2
QY1
QY0
QY4
QY4
QY5
QY6
QY7
QY6
QY5
QY7
PE
1
Pin numbers shown are for DW and NT packages.
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