SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Members of the Texas Instruments
SCOPE

Family of Testability Products

Octal Test-Integrated Circuits

Functionally Equivalent to 'F240 and
'BCT240 in the Normal-Function Mode

Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

Test Operation Synchronous to Test
Access Port (TAP)

Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V ) on TMS Pin

SCOPE

Instruction Set

 IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,
and HIGHZ

Parallel-Signature Analysis at Inputs
Pseudo-Random Pattern Generation

From Outputs

 Sample Inputs/Toggle Outputs

Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
and Ceramic 300-mil DIPs (JT, NT)

description

The 'BCT8240A scan test devices with octal
buffers are members of the Texas Instruments
SCOPE

testability integrated-circuit family. This

family of devices supports IEEE Standard
1149.1-1990 boundary scan to facilitate testing of
complex circuit-board assemblies. Scan access
to the test circuitry is accomplished via the 4-wire
test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F240 and 'BCT240 octal buffers. The test
circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals
or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the
functional operation of the SCOPE

octal buffers.

In the test mode, the normal operation of the SCOPE

octal buffers is inhibited and the test circuitry is enabled

to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations, as described in IEEE Standard 1149.1-1990.

1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SCOPE is a trademark of Texas Instruments Incorporated.

1OE

1Y1
1Y2
1Y3
1Y4

GND

2Y1
2Y2
2Y3
2Y4

TDO
TMS

2OE
1A1
1A2
1A3
1A4
2A1
V

2A2
2A3
2A4
TDI
TCK

SN54BCT8240A . . . JT PACKAGE

SN74BCT8240A . . . DW OR NT PACKAGE

(TOP VIEW)

3 2 1 28 27

12 13

2A4
TDI
TCK
NC
TMS
TDO
2Y4

1A2
1A1

2OE

1OE

1Y1
1Y2

14 15 16 17 18

1Y3

1Y4

GND

2Y1

2Y2

2Y3

1A3

1A4

2A1

2A2

2A3

SN54BCT8240A . . . FK PACKAGE

(TOP VIEW)

NC No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output
(TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54BCT8240A is characterized for operation over the full military temperature range of 55

C to 125

The SN74BCT8240A is characterized for operation from 0

C to 70

FUNCTION TABLE

(normal mode, each buffer)

INPUTS

OUTPUT

logic symbol

SCAN

'BCT8240A

1A1

1Y1

TDI

TCK-IN

EN1

1A2

1Y2

TMS

TCK

EN2

TCK-OUT

1A3

1Y3

1A4

1Y4

2A1

2Y1

2A2

2Y2

2A3

2Y3

2A4

2Y4

2OE

1OE

TDO

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

DESCRIPTION

1A11A4,

2A12A4

Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if
left unconnected.

GND

Ground

1OE, 2OE

Normal-function output-enable inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high
level if left unconnected.

TCK

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces
TCK to a high level if left unconnected.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active
and is not driven from an external source.

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its
TAP-controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test
reset signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (VIHH), at TMS.

VCC

Supply voltage

1Y11Y4,

2Y12Y4

Normal-function data outputs. See function table for normal-mode logic.

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

test architecture

Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a
2-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.

As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow
in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register may be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuted.

For the 'BCT8240A, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.

The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected-data register may capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.

For the 'BCT8240A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.

On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

register overview

With the exception of the bypass register, any test register may be thought of as a serial-shift register with a
shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the
appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register
may be parallel loaded from a source specified by the current instruction. During the appropriate shift state
(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted
in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from
the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the three data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 2 lists the instructions supported by the 'BCT8240A. The even-parity feature specified for SCOPE

devices is not supported in this device. Bit 7 of the instruction opcode is a don't-care bit. Any instructions that
are defined for SCOPE

devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDO

TDI

Bit 7

(MSB)

Don't

Care

Bit 0

(LSB)

Figure 2. Instruction Register Order of Scan

data-register description

boundary-scan register

The boundary-scan register (BSR) is 18 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function output pin. The BSR is used 1) to store test
data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output
terminals, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or
externally at the device input terminals.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR may change during Run-Test/Idle as determined by the current instruction. The contents
of the BSR are not changed in Test-Logic-Reset.

The BSR order of scan is from TDI through bits 170 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE
SIGNAL

BSR BIT

NUMBER

DEVICE
SIGNAL

BSR BIT

NUMBER

DEVICE
SIGNAL

1OE

1A1

1Y1

2OE

1A2

1Y2

1A3

1Y3

1A4

1Y4

2A1

2Y1

2A2

2Y2

2A3

2Y3

2A4

2Y4

boundary-control register

The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction
to implement additional test operations not included in the basic SCOPE

instruction set. Such operations

include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.

TDO

TDI

Bit 0

(LSB)

Bit 1

(MSB)

Figure 3. Boundary-Control Register Order of Scan

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation.

During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in
Figure 4.

Bit 0

TDO

TDI

Figure 4. Bypass Register Order of Scan

instruction-register opcode description

The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of
each instruction.

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Table 2. Instruction-Register Opcodes

BINARY CODE

BIT 7

BIT 0

MSB

LSB

SCOPE OPCODE

DESCRIPTION

SELECTED DATA

REGISTER

MODE

X0000000

EXTEST/INTEST

Boundary scan

Test

X0000001

BYPASS

Bypass scan

Bypass

Normal

X0000010

SAMPLE/PRELOAD

Sample boundary

Boundary scan

Normal

X0000011

INTEST/EXTEST

Boundary scan

Test

X0000100

BYPASS

Bypass scan

Bypass

Normal

X0000101

BYPASS

Bypass scan

Bypass

Normal

X0000110

HIGHZ (TRIBYP)

Control boundary to high impedance

Bypass

Modified test

X0000111

CLAMP (SETBYP)

Control boundary to 1/0

Bypass

Test

X0001000

BYPASS

Bypass scan

Bypass

Normal

X0001001

RUNT

Boundary run test

Bypass

Test

X0001010

READBN

Boundary read

Boundary scan

Normal

X0001011

READBT

Boundary read

Boundary scan

Test

X0001100

CELLTST

Boundary self test

Boundary scan

Normal

X0001101

TOPHIP

Boundary toggle outputs

Bypass

Test

X0001110

SCANCN

Boundary-control register scan

Boundary control

Normal

X0001111

SCANCT

Boundary-control register scan

Boundary control

Test

All others

BYPASS

Bypass scan

Bypass

Normal

Bit 7 is a don't-care bit; X = don't care.
The BYPASS instruction is executed in lieu of a SCOPE

instruction that is not supported in the 'BCT8240A.

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output terminals. The device operates in the test mode.

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device output terminals are placed in the high-impedance state,
the device input terminals remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output terminals. The device operates in the test mode.

boundary run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output
terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and
is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured
in the input BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 10, as shown in Table 3. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 3. Boundary-Control Register Opcodes

BINARY CODE

BIT 1

BIT 0

MSB

LSB

DESCRIPTION

Sample inputs/toggle outputs (TOPSIP)

Pseudo-random pattern generation/16-bit mode (PRPG)

Parallel-signature analysis/16-bit mode (PSA)

Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)

It should be noted, in general, that while the control input BSCs (bits 1716) are not included in the sample,
toggle, PSA, or PRPG algorithms, the output-enable BSCs (bits 1716 of the BSR) do control the drive state
(active or high impedance) of the selected device output terminals.

sample inputs / toggle outputs (TOPSIP)

Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each
rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs
of the normal on-chip logic. Data in the shift-register elements of the output BSCs is toggled on each rising edge
of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK.

pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK
and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK.
This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip
logic. Figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are
generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value
of all zeroes will not produce additional patterns.

1A1

1Y1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

Figure 5. 16-Bit PRPG Configuration

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

parallel-signature analysis (PSA)

Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register
elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input
BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs
remains constant and is applied to the device outputs. Figure 6 shows the 16-bit linear-feedback shift-register
algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before
performing this operation.

1A1

1Y1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

Figure 6. 16-Bit PSA Configuration

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 shows
the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An
initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes
will not produce additional patterns.

1A1

1Y1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

Figure 7. 8-Bit PSA / PRPG Configuration

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

timing description

All test operations of the 'BCT8240A are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs
is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals on the
falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the
value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is shown in Figure 8. In this example, the TAP controller begins in the Test-Logic-Reset
state and is advanced through its states, as necessary, to perform one instruction-register scan and one
data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO is used
to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 4 details the
operation of the test circuitry during each TCK cycle.

Table 4. Explanation of Timing Example

TCK

CYCLE(S)

TAP STATE

AFTER TCK

DESCRIPTION

Test-Logic-Reset

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.

Shift-IR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.

713

Shift-IR

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

Exit1-IR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

Update-IR

The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.

Select-DR-Scan

Capture-DR

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.

Shift-DR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.

1920

Shift-DR

The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

Exit1-DR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

Update-DR

In general, the selected data register is updated with the new data on the falling edge of TCK.

Select-DR-Scan

Select-IR-Scan

Test-Logic-Reset

Test operation completed

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

ÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎ

est-Logic-Reset

Run-T

est/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Update-IR

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Update-DR

Select-DR-Scan

Select-IR-Scan

est-Logic-Reset

TCK

TMS

TDI

TDO

ÎÎ

TAP

Controller

State

3-State (TDO) or Don't Care (TDI)

Figure 8. Timing Example

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

: except TMS (see Note 1)

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS (see Note 1)

0.5 V to 12 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the disabled or power-off state

0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state

0.5 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

30 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state: SN54BCT8240A (TDO)

40 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN54BCT8240A (any Y)

96 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74BCT8240A (TDO)

48 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74BCT8240A (any Y)

128 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at T

= 55

C (in still air) (see Note 2): DW package

1.7 W

. . . . . . . . . . . . . . . . . .

NT package

1.3 W

. . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input voltage rating may be exceeded if the input clamp-current rating is observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150

C and a board trace length of 750 mils,

except for the NT package, which has trace length of zero. For more information, refer to the

Package Thermal Considerations

application note in the

ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

recommended operating conditions

SN54BCT8240A

SN74BCT8240A

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

VIH

High-level input voltage

VIHH

Double-high-level input voltage

TMS

VIL

Low-level input voltage

0.8

IIK

Input clamp current

IOH

High level output current

TDO

IOH

High-level output current

Any Y

IOL

Low level output current

TDO

IOL

Low-level output current

Any Y

Operating free-air temperature

125

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

TEST CONDITIONS

SN54BCT8240A

SN74BCT8240A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

VIK

VCC = 4.5 V,

II = 18 mA

1.2

VCC = 4.75 V,

IOH = 3 mA

2.7

3.4

2.7

3.4

Any Y

IOH = 3 mA

2.4

3.4

2.4

3.4

Any Y

VCC = 4.5 V

IOH = 12 mA

3.2

VOH

IOH = 15 mA

3.1

VCC = 4.75 V,

IOH = 1 mA

2.7

3.4

2.7

3.4

TDO

VCC = 4 5 V

IOH = 1 mA

2.5

3.4

2.5

3.4

VCC = 4.5 V

IOH = 3 mA

2.4

3.3

2.4

3.3

Any Y

VCC = 4 5 V

IOL = 48 mA

0.38

0.55

VOL

Any Y

VCC = 4.5 V

IOL = 64 mA

0.42

0.55

VOL

TDO

VCC = 4 5 V

IOL = 20 mA

0.3

0.5

TDO

VCC = 4.5 V

IOL = 24 mA

0.35

0.5

VCC = 5.5 V,

VI = 5.5 V

0.1

IIH

VCC = 5.5 V,

VI = 2.7 V

100

IIHH

TMS

VCC = 5.5 V,

VI = 10 V

IIL

VCC = 5.5 V,

VI = 0.5 V

200

IOZH

Any Y

VCC = 5 5 V

VO = 2 7 V

IOZH

TDO

VCC = 5.5 V,

VO = 2.7 V

100

IOZL

Any Y

VCC = 5 5 V

VO = 0 5 V

IOZL

TDO

VCC = 5.5 V,

VO = 0.5 V

200

IOZPU

VCC = 0 to 2 V,

VO = 0.5 V or 2.7 V

250

IOZPD

VCC = 2 V to 0,

VO = 0.5 V or 2.7 V

250

Ioff

VCC = 0,

VI or VO

4.5 V

250

IOS

VCC = 5.5 V,

VO = 0

100

225

100

225

Outputs high

3.5

7.5

3.5

7.5

ICC

VCC = 5.5 V,

Outputs open

Outputs low

Outputs disabled

1.5

3.5

1.5

3.5

VCC = 5 V,

VI = 2.5 V or 0.5 V

VCC = 5 V,

VO = 2.5 V or 0.5 V

All typical values are at VCC = 5 V, TA = 25

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 9)

VCC = 5 V,

TA = 25

SN54BCT8240A

SN74BCT8240A

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

TCK

MHz

Pulse duration

TCK high or low

Pulse duration

TMS double high

50*

Any A before TCK

Setup time

Any OE before TCK

tsu

Setup time

TDI before TCK

TMS before TCK

Any A after TCK

4.5

Hold time

Any OE after TCK

4.5

Hold time

TDI after TCK

4.5

TMS after TCK

Delay time

Power up to TCK

100*

100

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 9)

PARAMETER

FROM

(INPUT)

(OUTPUT)

VCC = 5 V,

TA = 25

SN54BCT8240A

SN74BCT8240A

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

tPLH

2.5

5.7

7.5

2.5

tPHL

2.5

5.2

2.5

tPZH

9.5

tPZL

3.5

tPHZ

2.5

tPLZ

2.5

5.5

2.5

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 9)

PARAMETER

FROM

(INPUT)

(OUTPUT)

VCC = 5 V,

TA = 25

SN54BCT8240A

SN74BCT8240A

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

TCK

MHz

tPLH

TCK

15.5

21.5

tPHL

TCK

12.5

15.5

21.5

tPLH

TCK

TDO

3.5

7.6

10.5

3.5

tPHL

TCK

TDO

3.5

10.5

3.5

tPLH

TCK

7.5

16.5

7.5

tPHL

TCK

7.5

tPZH

TCK

6.5

tPZL

TCK

tPZH

TCK

TDO

3.5

7.6

10.5

3.5

11.5

3.5

tPZL

TCK

TDO

8.5

13.5

12.5

tPZH

TCK

tPZL

TCK

tPHZ

TCK

tPLZ

TCK

tPHZ

TCK

TDO

11.5

12.5

tPLZ

TCK

TDO

7.5

tPHZ

TCK

18.5

tPLZ

TCK

18.5

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS

SCBS067E FEBRUARY 1990 REVISED DECEMBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

Test
Point

(see Note A)

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

LOAD CIRCUIT FOR

3-STATE AND OPEN-COLLECTOR OUTPUTS

7 V (tPZL, tPLZ, O.C.)

Open
(all others)

From Output

Under Test

Test
Point

(see Note A)

RL = R1 = R2

1.5 V

3 V

0 V

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing Input

Data Input

1.5 V

3 V

0 V

High-Level

Pulse

Low-Level

Pulse

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V

tPHL

tPLH

tPHL

Input

Out-of-Phase

Output

1.5 V

3 V

0 V

VOL

VOH

VOL

In-Phase

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (see Note D)

tPHZ

tPLZ

0.3 V

tPZL

tPZH

1.5 V

3 V

0 V

Output

Control

(low-level enable)

Waveform 1

(see Note B)

Waveform 2

(see Note B)

0 V

VOH

VOL

3.5 V

0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, tr = tf

2.5 ns, duty cycle = 50%.

D. The outputs are measured one at a time with one transition per measurement.

E. When measuring propagation delay times of 3-state outputs, switch S1 is open.

Figure 9. Load Circuits and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

5962-9174601Q3A

ACTIVE

LCCC

TBD

Call TI

Level-NC-NC-NC

5962-9174601QLA

ACTIVE

CDIP

TBD

Call TI

Level-NC-NC-NC

SN74BCT8240ADW

ACTIVE

SOIC

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74BCT8240ADWE4

ACTIVE

SOIC

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74BCT8240ADWR

ACTIVE

SOIC

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74BCT8240ADWRE4

ACTIVE

SOIC

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74BCT8240ANT

ACTIVE

PDIP

Pb-Free

(RoHS)

CU NIPDAU

Level-NC-NC-NC

SN74BCT8240ANTE4

ACTIVE

PDIP

Pb-Free

(RoHS)

CU NIPDAU

Level-NC-NC-NC

SNJ54BCT8240AFK

ACTIVE

LCCC

TBD

Call TI

Level-NC-NC-NC

SNJ54BCT8240AJT

ACTIVE

CDIP

TBD

Call TI

Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

26-Sep-2005

Addendum-Page 1

MECHANICAL DATA

MCER004A JANUARY 1995 REVISED JANUARY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

JT (R-GDIP-T**)

CERAMIC DUAL-IN-LINE

24 LEADS SHOWN

4040110/C 08/96

0.200 (5,08) MAX

0.320 (8,13)
0.290 (7,37)

0.130 (3,30) MIN

0.008 (0,20)

0.014 (0,36)

Seating Plane

0.030 (0,76)

0.070 (1,78)

0.015 (0,38) MIN

0.100 (2,54) MAX

0.023 (0,58)
0.015 (0,38)

0.100 (2,54)

15

1.440

(37,08)

1.460

0.285

(7,39)

0.291

(36,58)

(7,24)

PINS **

1.280

1.240

0.300

0.245

(7,62)

DIM

B MAX

A MAX

A MIN

B MIN

(6,22)

(32,51)

(31,50)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB

MECHANICAL DATA

MLCC006B OCTOBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

4040140 / D 10/96

28 TERMINAL SHOWN

0.358

(9,09)

MAX

(11,63)

0.560

(14,22)

0.560

0.458

0.858

(21,8)

1.063

(27,0)

(14,22)

NO. OF

MIN

MAX

0.358

0.660

0.761

0.458

0.342

(8,69)

MIN

(11,23)

(16,26)

0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)

0.938

(28,99)

1.141

(24,43)

(29,59)

(19,32)

(18,78)

0.020 (0,51)

TERMINALS

0.080 (2,03)
0.064 (1,63)

(7,80)

0.307

(10,31)

0.406

(12,58)

0.495

(12,58)

0.495

(21,6)

0.850

(26,6)

1.047

0.045 (1,14)

0.035 (0,89)

0.010 (0,25)

0.020 (0,51)
0.010 (0,25)

B SQ

A SQ

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)
0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.

E. Falls within JEDEC MS-004

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2005, Texas Instruments Incorporated

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SN54BCT8240A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SN54BCT8240A