CDC318
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS587B JANUARY 1997 REVISED MARCH 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
High-Speed, Low-Skew 1-to-18 Clock Buffer
for Synchronous DRAM (SDRAM) Clock
Buffering Applications
D
Output Skew, t
sk(o)
, Less Than 250 ps
D
Pulse Skew, t
sk(p)
, Less Than 650 ps
D
Supports up to Four Unbuffered SDRAM
Dual Inline Memory Modules (DIMMs)
D
I
2
C Serial Interface Provides Individual
Enable Control for Each Output
D
Operates at 3.3 V
D
Distributed V
CC
and Ground Pins Reduce
Switching Noise
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Packaged in 48-Pin Shrink Small Outline
(DL) Package
description
The CDC318 is a high-performance clock buffer
that distributes one input (A) to 18 outputs (Y) with
minimum skew for clock distribution. The CDC318
operates from a 3.3-V power supply, and is
characterized for operation from 0
C to 70
C.
The device provides a standard mode
(100K-bits/s) I
2
C serial interface for device
control. The implementation is as a slave/receiver.
The device address is specified in the I
2
C device
address table. Both of the I
2
C inputs (SDATA and
SCLOCK) provide integrated pullup resistors
(typically 140 k
) and are 5-V tolerant.
Three 8-bit I
2
C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC318 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
V
CC
1Y0
1Y1
GND
V
CC
1Y2
1Y3
GND
A
V
CC
2Y0
2Y1
GND
V
CC
2Y2
2Y3
GND
V
CC
5Y0
GND
V
CC
SDATA
NC
NC
V
CC
4Y3
4Y2
GND
V
CC
4Y1
4Y0
GND
OE
V
CC
3Y3
3Y2
GND
V
CC
3Y1
3Y0
GND
V
CC
5Y1
GND
GND
SCLOCK
NC No internal connection
Intel is a trademark of Intel Corporation
CDC318
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS587B JANUARY 1997 REVISED MARCH 1998
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
OE
A
1Y01Y3
2Y02Y3
3Y03Y3
4Y04Y3
5Y05Y1
L
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
L
L
L
L
L
L
H
H
H
H
H
H
H
The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled
via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input.
logic diagram (positive logic)
1Y01Y3
2Y02Y3
3Y03Y3
4Y04Y3
5Y05Y1
OE
SDATA
SCLOCK
A
I2C
Register
Space
I2C
38
24
25
11
4, 5, 8, 9
13, 14, 17, 18
31, 32, 35, 36
40, 41, 44, 45
21, 28
18
/
CDC318
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS587B JANUARY 1997 REVISED MARCH 1998
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
1Y01Y3
4, 5, 8, 9
O
3.3-V SDRAM byte 0 clock outputs
2Y02Y3
13, 14, 17, 18
O
3.3-V SDRAM byte 1 clock outputs
3Y03Y3
31, 32, 35, 36
O
3.3-V SDRAM byte 2 clock outputs
4Y04Y3
40, 41, 44, 45
O
3.3-V SDRAM byte 3 clock outputs
5Y05Y1
21, 28
O
3.3-V clock outputs provided for feedback control of external phase-locked loops (PLLs)
A
11
I
Clock input
OE
38
I
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-k
pullup resistor is internally integrated.
SCLOCK
25
I
I2C serial clock input. A nominal 140-k
pullup resistor is internally integrated.
SDATA
24
I/O
Bidirectional I2C serial data input/output. A nominal 140-k
pullup resistor is internally
integrated.
GND
6, 10, 15, 19, 22, 26,
27, 30, 34, 39, 43
Ground
NC
1, 2, 47, 48
No internal connection. Reserved for future use.
VCC
3, 7, 12, 16, 20, 23,
29, 33, 37, 42, 46
3.3-V power supply
I2C DEVICE ADDRESS
A7
A6
A5
A4
A3
A2
A1
A0 (R/W)
H
H
L
H
L
L
H
--
I2C BYTE 0-BIT DEFINITION
BIT
DEFINITION
DEFAULT VALUE
7
2Y3 enable (pin 18)
H
6
2Y2 enable (pin 17)
H
5
2Y1 enable (pin 14)
H
4
2Y0 enable (pin 13)
H
3
1Y3 enable (pin 9)
H
2
1Y2 enable (pin 8)
H
1
1Y1 enable (pin 5)
H
0
1Y0 enable (pin 4)
H
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
CDC318
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS587B JANUARY 1997 REVISED MARCH 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I2C BYTE 1-BIT DEFINITION
BIT
DEFINITION
DEFAULT VALUE
7
4Y3 enable (pin 45)
H
6
4Y2 enable (pin 44)
H
5
4Y1 enable (pin 41)
H
4
4Y0 enable (pin 40)
H
3
3Y3 enable (pin 36)
H
2
3Y2 enable (pin 35)
H
1
3Y1 enable (pin 32)
H
0
3Y0 enable (pin 31)
H
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
I2C BYTE 2-BIT DEFINITION
BIT
DEFINITION
DEFAULT VALUE
7
5Y1 enable (pin 28)
H
6
5Y0 enable (pin 21)
H
5
Reserved
H
4
Reserved
H
3
Reserved
H
2
Reserved
H
1
Reserved
H
0
Reserved
H
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
CDC318
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS587B JANUARY 1997 REVISED MARCH 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(SCLOCK, SDATA) (see Note 1)
0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(SDATA) (see Note 1)
0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
0.5 V to V
CC
+0.5 V
. . . . . . . . . . . . .
Current into any output in the low state (except SDATA), I
O
48
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into SDATA in the low state, I
O
12
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) (SCLOCK)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) (SDATA)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Notes 2 and 3)
84
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
_
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero. The absolute maximum power dissipation allowed at TA = 55
C (in still air) is 1.2 W.
3. Thermal impedance (
JA) can be considerably lower if the device is soldered on the PCB board with a copper layer underneath the
package. A simulation on a PCB board (3 in.
3 in.) with two internal copper planes (1 oz. cu, 0.036 mm thick) and 0.071 mm cu
(202) in area underneath the package, resulted in
JA = 60
C/W. This would allow 1.2 W total power dissipation at TA = 70
C.
recommended operating conditions (see Note 4)
MIN
TYP
MAX
UNIT
VCC
3.3-V core supply voltage
3.135
3.465
V
A, OE
2
VCC+0.3
V
VIH
High-level input voltage
SDATA, SCLOCK
(see Note 3)
2.2
5.5
V
A, OE
0.3
0.8
V
VIL
Low-level input voltage
SDATA, SCLOCK
(see Note 3)
0
1.04
V
IOH
High-level output current
Y outputs
1
mA
IOL
Low-level output current
Y outputs
1
mA
ri
Input resistance to VCC
SDATA, SCLOCK
(see Note 3)
140
k
f(SCL)
SCLOCK frequency
100
kHz
t(BUS)
Bus free time
4.7
s
tsu(START)
START setup time
4.7
s
th(START)
START hold time
4
s
tw(SCLL)
SCLOCK low pulse duration
4.7
s
tw(SCLH)
SCLOCK high pulse duration
4
s
tr(SDATA)
SDATA input rise time
1000
ns
tf(SDATA)
SDATA input fall time
300
ns
tsu(SDATA)
SDATA setup time
250
ns
th(SDATA)
SDATA hold time
0
ns
tsu(STOP)
STOP setup time
4
s
TA
Operating free-air temperature
0
70
C
NOTE 4: The CMOS-level inputs fall within these limits: VIH min = 0.7
VCC and VIL max = 0.3
VCC.
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