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ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 AUGUST 1985 REVISED JUNE 1986
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
D
8-Bit Resolution
D
Easy Microprocessor interface or
Stand-Alone Operation
D
Operates Ratiometrically or With 5-V
Reference
D
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
D
Input Range 0 to 5 V With Single 5-V Supply
D
Inputs and Outputs Are Compatible With
TTL and MOS
D
Conversion Time of 32
s at CLK = 250 kHz
D
Designed to Be interchangeable With
National Semiconductor ADC0831 and
ADC0832
DEVICE
TOTAL UNADJUSTED ERROR
DEVICE
A-SUFFIX
B-SUFFIX
ADC0831
1 LSB
1/2 LSB
ADC0832
1 LSB
1/2 LSB
description
These devices are 8-bit successive-approximation analog-to-digital converters. The ADC0831A and
ADC0831B have single input channels; the ADC0832A and ADC0832B have multiplexed twin input channels.
The serial output is configured to interface with standard shift registers or microprocessors. Detailed information
on interfacing to most popular microprocessors is readily available from the factory.
The ADC0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition,
the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits
of resolution.
The operation of the ADC0831 and ADC0832 devices is very similar to the more complex ADC0834 and
ADC0838 devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum
analog input signal value, which gives the highest possible conversion resolution. Typically, REF is set equal
to V
CC
(done internally on the ADC0832). For more detail on the operation of the ADC0831 and ADC0832
devices, refer to the ADC0834/A DC0838 data sheet.
The ADC0831AC, ADC0831BC, ADC0832AC, and ADC0832BC are characterized for operation from 0
C
to 70
C. The ADC0831AI, ADC0831BI, ADC0832AI, and ADC0832BI are characterized for operation from
40
C to 85
C.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
8
7
6
5
CS
IN+
IN
GND
V
CC
CLK
DO
REF
ADC0831 . . . P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
CS
CH0
CH1
GND
V
CC
/REF
CLK
DO
DI
ADC0832 . . . P PACKAGE
(TOP VIEW)
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 AUGUST 1985 REVISED JUNE 1986
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
functional block diagram
R
Start
Flip-Flop
S
CLK
CLK
Time
Delay
S
R
CS
DO
CS
CS
D
CLK
R
EOC
9-Bit
Shift
Register
CS
R
CLK
First
LSB
Bit 1
Bits 07
First
One
Shot
SAR
Logic
and
Latch
R
EN
CS
Bits 07
REF
Ladder
and
Decoder
EN
Comparator
EN
Analog
Mux
CH1/IN
CH0/IN+
Single/Differential
Odd/Even
Start
CLK
D
Shift Register
To Internal
Circuits
(ADC0832
Only)
DI
CS
CLK
MSB
(ADC0831
Only)
7
1
5
5
1
1
1
1
1
6
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 AUGUST 1985 REVISED JUNE 1986
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
sequence of operation
Don't Care
1
7
6
2
0
1
2
6
7
MSB
LSB
LSB-First Data
Even
Dif
+Sign
Odd
SGL
Start
Bit
1
7
6
5
2
4
3
MSB
DI
DO
CS
tsu
CLK
21
20
19
18
14
13
12
1
2
3
4
5
6
10
11
ADC0832
Hi-Z
0
LSB
tconv
MSB-First Data
MSB
HI-Z
DO
MUX
Settling Time
CS
CLK
10
9
8
7
6
5
4
3
2
1
tsu
tconv
ADC0831
Hi-Z
MSB-First Data
ADC0832 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
CHANNEL NUMBER
SGL/DIF
ODD/EVEN
0
1
L
H
L
H
L
L
H
H
+
+
+
+
MUX
Settling Time
H = high level, L = low level,
or + = polarity of selected input pin
(ADC0832
only)
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 AUGUST 1985 REVISED JUNE 1986
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)
Supply voltage, V
CC
(see Note 1)
6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: Logic
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog
0.3 V to V
CC
+ 0.3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current
5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total input current for package
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: C-suffix
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix 40
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
6.3
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
fclock
Clock frequency
10
400
kHz
Clock duty cycle (see Note 2)
40
60
%
twH(C
S)
Pulse duration, CS high
220
ns
tsu
Setup time, CS low or ADC0832 data valid before CLK
350
ns
th
Hold time, ADC0832 data valid after CLK
90
ns
TA
Operating free air temperature
C-suffix
0
70
C
TA
Operating free-air temperature
I-suffix
40
85
C
NOTE 2: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low) is 1
s.
electrical characteristics over recommended range of operating free-air temperature, V
CC
= 5 V,
f
clock
= 250 kHz (unless otherwise noted)
digital section
PARAMETER
TEST CONDITIONS
{
C SUFFIX
I SUFFIX
UNIT
PARAMETER
TEST CONDITIONS
{
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VOH
High level output voltage
VCC = 4.75 V, IOH = 360
A
2.8
2.4
V
VOH
High-level output voltage
VCC = 4.75 V, IOH = 10
A
4.6
4.5
V
VOL
Low-levl output voltage
VCC = 4.75 V, IOL = 1.6 mA
0.34
0.4
V
IIH
High-level input current
VIH = 5 V
0.005
1
0.005
1
A
IIL
Low-level input current
VIL = 0
0.005
1
0.005
1
A
IOH
High-level output (source) current
VOH = VO,
TA = 25
C
6.5
14
6.5
14
mA
IOL
Low-level output (sink) current
VOL = VCC,
TA = 25
C
8
16
8
16
mA
IOZ
High-impedance-state output
VO = 5 V,
TA = 25
C
0.01
3
0.01
3
A
IOZ
g
current (DO)
VO = 0,
TA = 25
C
0.01
3
0.01
3
A
Ci
Input capacitance
5
5
pF
Co
Output capacitance
5
5
pF
All parameters are measured under open-loop conditions with zero common-mode input voltage.
All typical values are at VCC = 5 V, TA = 25
C.
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 AUGUST 1985 REVISED JUNE 1986
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
electrical characteristics over recommended range of operating free-air temperature,
V
CC
= 5 V, f
clock
= 250 kHz (unless otherwise noted)
analog and converter section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VICR
Common-mode input voltage range
See Note 3
0.05
to
VCC+ 0.05
V
On-channel
VI = 5 V
1
II( tdb )
Standby input current (see Note 4)
Off-channel
VI = 0
1
A
II(stdby)
Standby input current (see Note 4)
On-channel
VI = 0
1
A
Off-channel
VI = 5 V
1
ri(REF)
Input resistance to reference ladder
1.3
2.4
5.9
k
total device
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC
Supply current
ADC0831
1
2.5
mA
ICC
Supply current
ADC0832
3
5.2
mA
All parameters are measured under open-loop conditions with zero common-mode input voltage.
All typical values are at VCC = 5 V, TA = 25
C.
NOTES:
3. If channel IN is more positive than channel IN+, the digital output code will be 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC .Care must be taken during testing
at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause this input diode
to conduct and cause errors for analog inputs that are near full-scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V to 5 V input voltage range requires a minimum
VCC of 4.95 V for all variations of temperature and load.
4. Standby input currents are currents going into or out of the on or off channels when the A/D converter is not performing conversion
and the clock is in a high or low steady-state condition.
operating characteristics V
CC
= REF = 5 V, f
clock
= 250 kHz, t
r
= t
f
= 20 ns, T
A
= 25
C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
AI, AC SUFFIX
BI, BC SUFFIX
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Supply-voltage variation error
VCC = 4.75 V to 5.25 V
1/16
1/4
1/16
1/4
LSB
Total unadjusted error (see Note 5)
Vref = 5 V,
TA = MIN to MAX
1
1/2
LSB
Common-mode error
Differential mode
1/16
1/4
1/16
1/4
LSB
t d
Propagation delay time,
ouput data after CLK
MSB-first data
CL = 100 pF
650
1500
650
1500
ns
tpd
ouput data after CLK
(see Note 6)
LSB-first data
CL = 100 pF
250
600
250
600
ns
tdi
Output disable time,
CL = 10 pF, RL = 10 k
125
250
125
250
ns
tdis
,
DO after CS
CL = 100 pF, RL = 2 k
500
500
ns
tconv
Conversion time (multiplexer addressing
time not included)
8
8
clock
periods
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES:5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The most significant-bit-first data is output directly from the comparator and therefore requires additional delay to allow for comparator response
time. Least-significant-bit-first data applies only to ADC0832.
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