1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
GBA
CAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CBA
SBA
DW OR NT PACKAGE
(TOP VIEW)
74ACT11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS134 D3445, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
1
Inputs Are TTL-Voltage Compatible
Bus Transceivers/Registers
Independent Registers and Enables for A
and B Buses
Multiplexed Real-Time and Stored Data
Inverting Data Paths
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic Small
Outline Packages and Standard Plastic
300-mil DIPs
description
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the internal storage registers. Enables GAB and GBA
are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether
real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch
that occurs in a multiplexer during the transition between stored and real-time data.
A low input level selects real-time data and a high selects stored data. Figure 1 illustrates the four fundamental
bus-management functions that can be performed with the octal bus transceivers and registers. Data on the
A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock
pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time
transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously
enabling GAB and GBA. In this configuration, each output reinforces its input. Thus, when all other data sources
to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
The 74ACT11651 is characterized for operation from 40
C to 85
C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74ACT11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS134 D3445, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
BUS A
BUS B
BUS A
BUS B
GAB
GBA
CAB
CBA
SAB
SBA
GAB
GBA
CAB
CBA
SAB
SBA
L
L
X
X
X
L
H
H
X
X
L
X
REAL-TIME TRANSFER BUS B TO BUS A
REAL-TIME TRANSFER BUS A TO BUS B
BUS A
BUS B
BUS A
BUS B
GAB
GBA
CAB
CBA
SAB
SBA
GAB
GBA
CAB
CBA
SAB
SBA
X
H
X
X
X
H
L
H or L
H or L
H
H
L
X
X
X
X
L
H
X
X
STORAGE FROM A AND/OR B
TRANSFER STORED DATA TO A AND/OR B
Figure 1. Bus Transfer Diagram
74ACT11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS134 D3445, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
GAB
GBA
CAB
CBA
SAB
SBA
A1 THRU A8
B1 THRU B8
OPERATION OR FUNCTION
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
X
X
Input
Input
Store A and B Data
X
H
H or L
X
X
Input
Unspecified
Store A, Hold B
H
H
X
X
Input
Output
Store A in both registers
L
X
H or L
X
X
Unspecified
Input
Hold A, Store B
L
L
X
X
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-Time B data to A Bus
L
L
X
H or L
X
H
Output
Input
Stored B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Input
Output
Stored A Data to B Bus
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers.
logic symbol
5
5
B8
B7
B6
B5
B4
B3
B2
B1
17
18
19
20
23
24
25
26
A8
A7
A6
A5
A4
A3
A2
A1
SAB
CAB
SBA
CBA
GBA
GAB
13
12
11
10
5
4
3
2
27
28
15
16
14
1
1
6D
7
7
4D
G7
C6
G5
C4
EN2 [AB]
EN1 [BA]
2
1
1
1
1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
74ACT11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS134 D3445, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
logic diagram (positive logic)
TG
TG
To Channel 1 Above
7 Channels Identical
B8
B7
B6
B5
17
18
19
20
23
24
25
B4
B3
B2
26
2
27
28
15
16
1
14
SAB
A1
CAB
SBA
CBA
GAB
GBA
13
12
11
10
5
4
3
C1
1D
TG
TG
1D
C1
A2
A3
A4
A5
A6
A7
A8
B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74ACT11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS134 D3445, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t/
D
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
OH
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
{
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
OL
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
{
5.5 V
1.65
IOZ
A or B ports
VI = VCC or GND
5.5 V
0.5
5
m
A
II
Control Inputs
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
80
m
A
D
ICC
VI = VCC or GND
5.5 V
0.9
1
mA
Ci
Control Inputs
VI = VCC or GND
5 V
4.5
pF
Cio
A or B ports
VI = VCC or GND
5 V
10
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
90
0
100
MHz
tw
Pulse duration, CAB or CBA high or low
5.5
5
ns
tsu
Setup time, A before CAB
or B before CBA
4.5
4.5
ns
th
Hold time, A after CAB
or B after CBA
2
0
ns
74ACT11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS134 D3445, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
90
90
MHz
tPLH
A or B
B or A
2.6
5.6
8.9
2.6
9.9
ns
tPHL
A or B
B or A
4.7
7.7
10.7
4.7
11.9
ns
tPLH
CBA or CAB
A or B
5.5
8.4
11.2
5.5
12.7
ns
tPHL
CBA or CAB
A or B
6.3
9.5
12.7
6.3
14.1
ns
tPLH
SBA or SAB
A or B
4.8
7.6
10.4
4.8
11.8
ns
tPHL
with A or B high
A or B
4.1
7.7
11.2
4.1
12.4
ns
tPLH
SBA or SAB
A or B
3
6.2
9.3
3
10.4
ns
tPHL
with A or B low
A or B
5.6
8.7
11.7
5.6
13
ns
tPZH
GBA
A
4
7.4
10.7
4
11.9
ns
tPZL
GBA
A
4.3
8.2
11.9
4.3
13.3
ns
tPHZ
GBA
A
5.9
7.7
9.5
5.9
10
ns
tPLZ
GBA
A
5.1
6.9
8.7
5.1
9.2
ns
tPZH
GAB
B
5.9
9
12.1
5.9
13.7
ns
tPZL
GAB
B
6.4
9.8
13.2
6.4
14.9
ns
tPHZ
GAB
B
4.7
7.1
9.5
4.7
10
ns
tPLZ
GAB
B
3.8
6.1
8.4
3.8
8.8
ns
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per gate
Outputs enabled
CL = 50 pF
f = 1 MHz
61
pF
Cpd Power dissipation capacitance per gate
Outputs disabled
CL = 50 pF, f = 1 MHz
15
pF
74ACT11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS134 D3445, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
LOAD CIRCUIT FOR OUTPUTS
S1
2
VCC
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
VCC
GND
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
VCC
0 V
50% VCC
0 V
3 V
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
(see Note A)
50% VCC
20% VCC
80% VCC
tPLH
tPHL
1.5 V
1.5 V
0 V
50% VCC
50% VCC
VOH
VOL
Input
(see Note B)
Output
(see Note D)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
3 V
3 V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
PDF 
ZIP