ST93C46A,46C,46T
ST93C47C,47T
1K (64 x 16 or 128 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
June 1997
1/13
This is information on a product still in production bu t not recommended for new de signs.
AI00871C
D
VCC
ST93C46
ST93C47
VSS
C
Q
S
ORG
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 64 x 16 or 128 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE:
4.5V to 5.5V for ST93C46 version
3V to 5.5V for ST93C47 version
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
PERFORMANCE for "C" VERSION
ST93C46A, ST93C46C, ST93C46T,
ST93C47C, ST93C47T are replaced by the
M93C46
DESCRIPTION
This specification covers a range of 1K bit serial
EEPROM products, the ST93C46A,46C,46T
specified at 5V
10% and the ST93C47C,47T
specified at 3V to 5.5V.
In the text, products are referred to as ST93C46.
The ST93C46 is a 1K bit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
SGS-THOMSON's High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
through a serial input (D) and output (Q).
S
Chip Select Input
D
Serial Data Input
Q
Serial Data Output
C
Serial Clock
ORG
Organisation Select
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
8
1
SO8 (M)
150mil Width
8
1
PSDIP8 (B)
0.4mm Frame
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 125
C
T
STG
Storage Temperature
65 to 150
C
T
LEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
C
V
IO
Input or Output Voltages (Q = V
OH
or Hi-Z)
0.3 to V
CC
+0.5
V
V
CC
Supply Voltage
0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
(2)
ST93C46A,T
ST93C46C
2000
4000
V
Electrostatic Discharge Voltage (Machine model)
(3)
ST93C46
500
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
).
3. EIAJ IC-121 (Condition C) (200pF, 0
).
Table 2. Absolute Maximum Ratings
(1)
1
VSS
Q
ORG
DU
C
S
VCC
D
AI00874C
ST93C46
ST93C47
2
3
4
8
7
6
5
Figure 2B. SO Pin Connections
Warning: DU = Don't Use
VSS
Q
ORG
DU
C
S
VCC
D
AI00872C
ST93C46
ST93C47
1
2
3
4
8
7
6
5
Figure 2A. DIP Pin Connections
Warning: DU = Don't Use
1
D
C
Q
VSS
VCC
DU
ORG
S
AI00982B
ST93C46T
ST93C47T
2
3
4
8
7
6
5
Figure 2C. SO, 90
Turn, Pin Connections
Warning: DU = Don't Use
The 1K bit memory is divided into either 128 x 8 bit
bytes or 64 x 16 bit words. The organization may
be selected by a signal on the ORG input. The
memory is accessed by a set of instructions which
includes Read a byte/word, Write a byte/word,
Erase a byte/word, Erase All and Write All.
A Read instruction loads the address of the first
byte/word to be read into an internal address
pointer. The data is then clocked out serially.
The address pointer is automatically incremented
after the data is output and, if the Chip Select input
(S) is held High, the ST93C46 can output a sequen-
tial stream of data bytes/words. In this way, the
memory can be read as a data stream from 8 to
1024 bits long, or continuously as the address
DESCRIPTION (cont'd)
2/13
ST93C46A/46C/46T, ST93C47C/47T
Input Rise and Fall Times
20ns
Input Pulse Voltages
0.4V to 2.4V
Input Timing Reference Voltages
1V to 2.0V
Output Timing Reference Voltages
0.8V to 2.0V
AC MEASUREMENT CONDITIONS
Note that Output Hi-Z is defined as the point where data
is no longer driven.
AI00815
2.4V
0.4V
2.0V
0.8V
2V
1V
INPUT
OUTPUT
Figure 3. AC Testing Input Output Waveforms
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5
pF
Note: 1. Sampled only, not 100% tested.
Table 3. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
2.5
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
,
Q in Hi-Z
2.5
A
I
CC
Supply Current (TTL Inputs)
S = V
IH
, f = 1 MHz
3
mA
Supply Current (CMOS Inputs)
S = V
IH
, f = 1 MHz
2
mA
I
CC1
Supply Current (Standby)
S = V
SS
, C = V
SS
,
ORG = V
SS
or V
CC
50
A
V
IL
Input Low Voltage (D, C, S)
V
CC
= 5V
10%
0.3
0.8
V
3V
V
CC
4.5V
0.3
0.2 V
CC
V
V
IH
Input High Voltage (D, C, S)
V
CC
= 5V
10%
2
V
CC
+ 1
V
3V
V
CC
4.5V
0.8 V
CC
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
I
OL
= 10
A
0.2
V
V
OH
Output High Voltage
I
OH
= 400
A
2.4
V
I
OH
= 10
A
V
CC
0.2
V
Table 4. DC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 4.5V to 5.5V or 3V to 5.5V)
3/13
ST93C46A/46C/46T, ST93C47C/47T
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
SHCH
t
CSS
Chip Select High to Clock High
50
ns
t
CLSH
t
SKS
Clock Low to Chip Select High
100
ns
t
DVCH
t
DIS
Input Valid to Clock High
100
ns
t
CHDX
t
DIH
Clock High to Input Transition
Temp. Range: grade 1
100
ns
Temp. Range:
grades 3, 6
200
ns
t
CHQL
t
PD0
Clock High to Output Low
500
ns
t
CHQV
t
PD1
Clock High to Output Valid
500
ns
t
CLSL
t
CSH
Clock Low to Chip Select Low
0
ns
t
SLCH
Chip Select Low to Clock High
250
ns
t
SLSH
t
CS
Chip Select Low to Chip Select High
Note 1
250
ns
t
SHQV
t
SV
Chip Select High to Output Valid
500
ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z
ST93C46A
300
ns
ST93C46C, 47C
200
ns
t
CHCL
t
SKH
Clock High to Clock Low
Note 2
250
ns
t
CLCH
t
SKL
Clock Low to Clock High
Note 2
250
ns
t
W
t
WP
Erase/Write Cycle time
10
ms
f
C
f
SK
Clock Frequency
0
1
MHz
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (t
SLSH
) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1
s, therefore the sum of the timings t
CHCL
+ t
CLCH
must be greater or equal to 1
s. For example, if t
CHCL
is 250 ns, then t
CLCH
must be at least 750 ns.
Table 5. AC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 4.5V to 5.5V or 3V to 5.5V)
AI01428
C
OP CODE
OP CODE
START
S
D
OP CODE INPUT
START
tDVCH
tSHCH
tCLSH
tCHCL
tCLCH
tCHDX
Figure 4. Synchronous Timing, Start and Op-Code Input
4/13
ST93C46A/46C/46T, ST93C47C/47T
Figure 5. Synchronous Timing, Read or Write
AI00820C
C
D
Q
ADDRESS INPUT
Hi-Z
tDVCH
tCLSL
A0
S
DATA OUTPUT
tCHQV
tCHDX
tCHQL
An
tSLSH
tSLQZ
Q15/Q7
Q0
AI01429
C
D
Q
ADDRESS/DATA INPUT
Hi-Z
tDVCH
tSLCH
A0/D0
S
WRITE CYCLE
tSLSH
tCHDX
An
tCLSL
tSLQZ
BUSY
tSHQV
tW
READY
counter automatically rolls over to '00' when the
highest address is reached.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 8 or 16 bits at one
time into one of the 128 bytes or 64 words. After
the start of the programming cycle a Busy/Ready
signal is available on the Data output (Q) when
Chip Select (S) is High.
An internal feature of the ST93C46 provides
Power-on Data Protection by inhibiting any opera-
tion when the Supply is too low. The design of the
ST93C46 and the High Endurance CMOS technol-
ogy used for its fabrication give an Erase/Write
cycle Endurance of 1,000,000 cycles and a data
retention of 40 years.
The DU (Don't Use) pin does not affect the function
of the memory and it is reserved for use by SGS-
THOMSON during test sequences.The pin may be
left unconnected or may be connected to V
CC
or
V
SS
. Direct connection of DU to V
SS
is recom-
mended for the lowest standby power consump-
tion.
DESCRIPTION (cont'd)
5/13
ST93C46A/46C/46T, ST93C47C/47T
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