January 2000

1/22

Rev. 2.5

ST92195B

32-64K ROM HCMOS MCU WITH

ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER

DATA BRIEFING

C to +70

C operating temperature range

Up to 24 MHz. operation @ 5V

10%

Min. instruction cycle time: 165ns at 24 MHz.

32, 48, 56 or 64 Kbytes ROM

256 bytes RAM of Register file (accumulators or
index registers)

256 bytes of on-chip static RAM

2, 6 or 8 Kbytes of TDSRAM (Teletext and
Display Storage RAM)

28 fully programmable I/O pins

Serial Peripheral Interface

Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.

Enhanced display controller with 26 rows of
40/80 characters

Serial and Parallel attributes

10x10 dot matrix, 512 ROM characters, defin-

able by user

4/3 and 16/9 supported in 50/60Hz and 100/

120 Hz mode

Rounding, fringe, double width, double height,

scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes

Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage

VPS and Wide Screen Signalling slicer (on
some devices)

Integrated Sync Extractor and Sync Controller

14-bit Voltage Synthesis for tuning reference
voltage

Up to 6 external interrupts plus one Non-
Maskable Interrupt

8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability

16-bit watchdog timer with 8-bit prescaler

One 16-bit standard timer with 8-bit prescaler

4-channel A/D converter; 5-bit guaranteed

Rich instruction set and 14 addressing modes

Versatile

development

tools,

including

Assembler,

Linker,

C-compiler,

Archiver,

Source

Level

Debugger

and

hardware

emulators with Real-Time Operating System
available from third parties

Pin-compatible EPROM and OTP devices
available

Device Summary

Device

Program

Memory

TDS

RAM

VPS/
WSS

Package

ST92195B1

32K ROM

Yes

PSDIP56/

TQFP64

ST92195B2

32K ROM

ST92195B3

32K ROM

Yes

ST92195B4

48K ROM

Yes

ST92195B5

48K ROM

Yes

ST92195B6

56K ROM

Yes

ST92195B7

64K ROM

Yes

ST92T195B7

64K OTP

Yes

ST92E195B7

64K EPROM

Yes

CSDIP56
/CQFP64

TQFP64

PSDIP56

See end of document for ordering information

2/22

ST92195B - GENERAL DESCRIPTION

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST92195B microcontroller is developed and

manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The ST92195B MCU supports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.

1.1.1 ST9+ Core

The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.

The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.

Two basic addressable spaces are available: the
Memory space and the Register File, which in-
cludes the control and status registers of the on-
chip peripherals.

1.1.2 Power Saving Modes

To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.

Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).

Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-

cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).

Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen

(the clock is

also

stopped). A reset is necessary to exit from Halt
mode.

1.1.3 I/O Ports

Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.

1.1.4 TV Peripherals

A set of on-chip peripherals form a complete sys-
tem for TV set and VCR applications:

Voltage Synthesis

VPS/WSS Slicer

Teletext Slicer

Teletext Display RAM

OSD

1.1.5 On Screen Display

The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 char-
acter set. The character resolution is 10x10 dot.
Four character sizes are supported. Serial at-
tributes allow the user to select foreground and
background colors, character size and fringe back-
ground. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.

1.1.6 Teletext and Display Storage RAM

The internal Teletext and Display storage RAM
can be used to store Teletext pages as well as Dis-
play parameters.

3/22

ST92195B - GENERAL DESCRIPTION

INTRODUCTION (Cont'd)

1.1.7 Teletext, VPS and WSS Data Slicers

The three on-board data slicers using a single ex-
ternal crystal are used to extract the Teletext, VPS
and WSS information from the video signal. Hard-
ware Hamming decoding is provided.

1.1.8 Voltage Synthesis Tuning Control

14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique can be used to generate tuning voltages
for TV set applications. The tuning voltage is out-
put on one of two separate output pins.

1.1.9 PWM Output

Control of TV settings can be made with up to
eight 8-bit PWM outputs, with a maximum frequen-
cy of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions with higher frequency oper-
ation can be programmed.

1.1.10 Serial Peripheral Interface (SPI)

The SPI bus is used to communicate with external
devices via the SPI, or I C bus communication
standards. The SPI uses a single data line for data
input and output. A second line is used for a syn-
chronous clock signal.

1.1.11 Standard Timer (STIM)

The ST92195B has one Standard Timer (STIM0)
that includes a programmable 16-bit down counter
and an associated 8-bit prescaler with Single and
Continuous counting modes.

1.1.12 Analog/Digital Converter (ADC)

In addition there is a 4-channel Analog to Digital
Converter with integral sample and hold, fast
5.75

s conversion time and 6-bit guaranteed reso-

lution.

4/22

ST92195B - GENERAL DESCRIPTION

INTRODUCTION (Cont'd)

Figure 1. ST92195B Block Diagram

MEMORY

BUS

I/O

PORT 0

BUS

VOLTAGE

SYNTHESIS

PWM

D/A CON-

VERTER

SPI

I/O

PORT 4

I/O

PORT 5

Up to 64

Kbytes ROM

DATA

SLICER

& ACQUI-

SITIO N

UNIT

SYNC.

EXTRAC-

TION

Up to 8

Kbytes

TDSRAM

TRI

256 bytes

RAM

STANDARD

TIMER

TIMI NG AND

CLOCK CTRL

16-BIT

TIMER/

WATCHDOG

VPS/WSS

DATA

SLICER

I/O

PORT 2

ADC

CVBS1

I/O

PORT 3

SYNC

CONTROL

VSYNC

HSYNC/CSYNC

SCREEN
DISPLAY

FREQ.

MULTIP.

PXFM

NMI

INT[7:4]

INT2

256 bytes

ST9+ CORE

8/16-bit

CPU

Interrupt

Management

RCCU

OSCIN

OSCOUT

RESET

RESETO

P0[7:0]

WSCR
WSCF
CVBS2

R/G/B/FB

PWM[7:0]

SDO/SDI

SCK

INT0

STOUT

MMU

MCFM

TXCF

TSLU

AIN[4:1]

VSO[2:1]

EXTRG

P2[5:0]

P4[7:0]

P5[1:0]

P3[7:4]

CSO

All alternate functions

(Italic characters)

are mapped on Ports 0, 2, 3, 4 and 5

6/22

ST92195B - GENERAL DESCRIPTION

PIN DESCRIPTION (Cont'd)

RESET

Reset (input, active low). The ST9+ is ini-

tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.

R/G/B

Red/Green/Blue. Video color analog DAC

outputs.

Fast Blanking. Video analog DAC output.

Main power supply voltage (5V

10%, digital)

WSCF, WSCR Analog pins for the VPS/WSS slic-
er . These pins must be tied to ground or not con-
nected.

: On EPROM/OTP devices, the WSCR pin is

replaced by V

which is the programming voltage

pin. V

should be tied to GND in user mode.

MCFM Analog pin for the display pixel frequency
multiplier.

OSCIN, OSCOUT

Oscillator (input and output).

These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.

VSYNC

Vertical Sync. Vertical video synchronisa-

tion input to OSD. Positive or negative polarity.

HSYNC/CSYNC

Horizontal/Composite sync. Hori-

zontal or composite video synchronisation input to
OSD. Positive or negative polarity.

PXFM Analog pin for the Display Pixel Frequency
Multiplier

AVDD3

Analog V

of PLL. This pin must be tied

to V

externally.

GND Digital circuit ground.

AGND Analog circuit ground (must be tied exter-
nally to digital GND).

CVBS1 Composite video input signal for the Tele-
text slicer and sync extraction.

CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.

AVDD1, AVDD2 Analog power supplies (must be
tied externally to AVDD3).

TXCF Analog pin for the Teletext slicer line PLL.

CVBSO, JTDO, JTCK Test pins: leave floating.

TEST0 Test pins: must be tied to AVDD2.

JTRST0 Test pin: must be tied to GND.

Figure 3. 56-Pin Package Pin-Out

INT7/P2.0

RESET

P0.7
P0.6
P0.5
P0.4
P0.3

AIN4/P0.2

P0.1
P0.0

CSO/RE SET0/P3.7

P3.6
P3.5
P3.4

SDI/SDO/ P5.1

SCK/INT2/P5. 0

JTDO

WSC F

/WSCR
AVDD3

TEST 0

MCFM

JTCK

P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4 /VS02
OSCIN
OSCOUT
P4.7/PWM7/EX TRG/ST OUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSL U/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRSTO
GND
AGND
CVBS 1
CVBS 2
JTMS
AVDD2
CVBS O

TXCF

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

7/22

ST92195B - GENERAL DESCRIPTION

PIN DESCRIPTION (Cont'd)

Figure 4. ST92195B Required External components (56-pin package)

+5V

P20

P24

P05

P50

P46

P37

P47

P04

P45

P03

P01

P44

P07

P36

P51

P21

P02

P00

P43

P41

P22

P35
P34

P25

P42

P40

P23

P06

C16

2.2nF

15k

C13

4.7nF

C10

4.7nF

82pF

5.6k

C14

82pF

C11

22pF

RST

1N4148

C12

470nF

22pF

100 nF

100nF

C15

100nF

10uH

10k

10uH

4Mhz

SDIP56

ST92195B

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

P2.0/INT7

P2.1/ INT5/AIN1

RESETN
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
B
G
R
FB
P5.1/SDI/SDO
P5.0/SCK/INT2
VDD
JTDO
WSCF
WSCR
AVDD3
TEST0
MCFM
JTCK

P2.2/ INT0/AIN2

P2.3/INT6 /VS01

P2.4/NMI

P2.5/AIN3/INT4/VS02

OSCIN

OSCOUT

P4.7/PWM7/EXTR G/STOUT

P4.6/PWM6
P4.5/PWM5
P4.4/PWM4

P4.3/PWM3 /TSLU/HT

P4.2/PWM2
P4.1/PWM1
P4.0/PWM0

VSYNC

HSY NC/CSYNC

AVDD1

PXFM

JTRST0

GND

AGND

CVBS1
CVBS2

JTMS

AVDD2

CVBSO

TXCF

CVBS

VSYNC

H SYNC

8/22

ST92195B - GENERAL DESCRIPTION

PIN DESCRIPTION (Cont'd)

Figure 5. ST92195B Required External Components (64-pin package)

+5V

P20

P25

P36

P05

P46

P03

P35

P40

P06

P45

P34

P42

P07

P44

P5.1

P37

P43

P21

P47

P24

P01

P41

P22

P00

P04

P02

P23

P5.0

5.6k

4Mhz

5.6k

10k

1N4148

10uH

C12

100nF

82pF

RST

C13

10uF

82pF

C15

4.7nF

10uF

100nF

C14

22pF

100nF

C10

4.7nF

C11

100nF

QFP64

ST92195B

2
3
4
5
6
7
8
9

10
11
12
13
14
15

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VSS

P2.1/INT5/AIN1

P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
B
G
R
F B
P5.1/SDI/SDO
P5.0/SCK/INT2
VDD

P2.2/INT0/AIN2

P2.3/INT6/VS01

P2.4/NMI

P2.5/AIN3/INT4/VS02

OSCIN

OSCOUT

VDD

GND

EXTRG/SLOUT/P4.7/PWM7

P4.6/PWM6
P4.5/PWM5

P4.4/PWM4

HT/TSLU/P4.3/PWM3

P4.2/PWM2
P4.1/PWM1
P4.0/PWM0

VSYNC

CSYNC/HSYNC

AVDD1

PXFM

JTRST0

GND

AGND

CVBS1

CVBS2

MCFM

WSCF

WSCR

AVDD3

TEST0

JTCK

TXCF

CVBSO

AVDD2

JTMS

JTDO

INT7/P2.0

RESETN

P0.7

P0.6

P0.5

P0.4

P0.3

VDD

R
FB

HSYNC

VSYNC

9/22

ST92195B - GENERAL DESCRIPTION

PIN DESCRIPTION (Cont'd)

P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]
I/O Port Lines (Input/Output, TTL or CMOS com-
patible).

28 lines grouped into I/O ports, bit programmable
as general purpose I/O or as Alternate functions
(see I/O section).

Important: Note that open-drain outputs are for
logic levels only and are not true open drain.

1.2.1 I/O Port Alternate Functions.

Each pin of the I/O ports of the ST92195B may as-
sume software programmable Alternate Functions
(see Table 1).

Table 1. ST92195B I/O Port Alternate Function Summary

Port

Name

General

Purpose I/O

Pin No.

Alternate Functions

TQFP64 SDIP56

P0.0

All ports useable
for general pur-
pose I/O (input,
output or bidi-
rectional)

I/O

P0.1

I/O

P0.2

AIN4

A/D Analog Data Input 4

P0.3

I/O

P0.4

I/O

P0.5

I/O

P0.6

I/O

P0.7

I/O

P2.0

INT7

External Interrupt 7

P2.1

AIN1

A/D Analog Data Input 1

INT5

External Interrupt 5

P2.2

INT0

External Interrupt 0

AIN2

A/D Analog Data Input 2

P2.3

INT6

External Interrupt 6

VSO1

Voltage Synthesis Output 1

P2.4

NMI

Non Maskable Interrupt Input

P2.5

AIN3

A/D Analog Data Input 3

INT4

External Interrupt 4

VSO2

Voltage Synthesis Output 2

P3.4

I/O

P3.5

I/O

P3.6

I/O

P3.7

RESET0

Internal Reset Output

CSO

Composite Sync output

P4.0

PWM0

PWM Output 0

P4.1

PWM1

PWM Output 1

P4.2

PWM2

PWM Output 2

P4.3

PWM3

PWM Output 3

TSLU

Translucency Digital Output

Half-tone Output

P4.4

PWM4

PWM Output 4

10/22

ST92195B - GENERAL DESCRIPTION

1.2.2 I/O Port Styles

Legend:

AF= Alternate Function, BID = Bidirectional, OD = Open Drain
PP = Push-Pull, TTL = TTL Standard Input Levels

How to Read this Table

To configure the I/O ports, use the information in
this table and the Port Bit Configuration Table in
the I/O Ports Chapter of the datasheet.

Port Style= the hardware characteristics fixed for
each port line.

Inputs:

If port style = Standard I/O, either TTL or CMOS

input level can be selected by software.

If port style = Schmitt trigger, selecting CMOS or

TTL input by software has no effect, the input will
always be Schmitt Trigger.

Weak Pull-Up = This column indicates if a weak
pull-up is present or not.

If WPU = yes, then the WPU can be enabled/dis-

able by software

If WPU = no, then enabling the WPU by software

has no effect

Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:

An alternate function can be selected as follows.

AF Inputs:

AF is selected implicitly by enabling the corre-

sponding peripheral. Exception to this are ADC
analog inputs which must be explicitly selected
as AF by software.

P4.5

All ports useable
for general pur-
pose I/O (input,
output or bidi-
rectional)

PWM5

PWM Output 5

P4.6

PWM6

PWM Output 6

P4.7

EXTRG

A/D Converter External Trigger Input

PWM7

PWM Output 7

STOUT

Standard Timer Output

P5.0

INT2

External Interrupt 2

SCK

SPI Serial Clock

P5.1

SDO

SPI Serial Data Out

SDI

SPI Serial Data In

Port

Name

General

Purpose I/O

Pin No.

Alternate Functions

TQFP64 SDIP56

Pins

Weak Pull-Up

Port Style

Reset Values

P0[7:0]

Standard I/O

BID / OD / TTL

P2[5,4,3,2]

Standard I/O

BID / OD / TTL

P2[1,0]

Schmitt trigger

BID / OD / TTL

P3.7

yes

Standard I/O

AF / PP / TTL

P3[6,5,4]

Standard I/O

BID / OD / TTL

P4[7:0]

Standard I/O

BID / OD / TTL

P5[1:0]

Standard I/O

BID / OD / TTL

11/22

ST92195B - GENERAL DESCRIPTION

PIN DESCRIPTION (Cont'd)

AF Outputs or Bidirectional Lines:

In the case of Outputs or I/Os, AF is selected

explicitly by software.

Example 1: ADC trigger digital input

AF: EXTRG, Port: P4.7, Port Style: Standard I/O.

Write the port configuration bits (for TTL level):

P4C2.7=1

P4C1.7=0

P4C0.7=1

Enable the ADC trigger by software as described
in the ADC chapter.

Example 2: PWM 0 output

AF: PWM0, Port: P4.0

Write the port configuration bits (for output push-
pull):

P4C2.0=0

P4C1.0=1

P4C0.0=1

Example 3: ADC analog input

AF: AIN1, Port : P2.1, Port style: does not apply to
analog inputs

Write the port configuration bits:

P2C2.1=1

P2C1.1=1

P2C0.1=1

12/22

ST92195B - GENERAL DESCRIPTION

1.3 MEMORY MAP

Internal ROM
The ROM memory is mapped in a single continu-
ous area starting at address 0000h in MMU seg-
ment 00h.

Internal RAM, 256 bytes
The internal RAM is mapped in MMU segment
20h; from address FF00h to FFFFh.

Internal TDSRAM
The Internal TDSRAM is mapped starting at ad-
dress 8000h in MMU segment 22h. It is a fully stat-
ic memory.

Figure 6. ST92195B Memory Map

Device

Size

Start

Address

End

Address

ST92195B1/B2/B3

32K

0000h

7FFFh

ST92195B4/B5

48K

0000h

BFFFh

ST92195B6

56K

0000h

DFFFh

ST92195B7

64K

0000h

FFFFh

Device

Size

Start

Address

End

Address

ST92195B1

8000h

87FFh

ST92195B2/B3/B4

8000h

97FFh

ST92195B5/B6/B7

8000h

9FFFh

SEGMENT 0

64 Kbytes

00FFFFh

00C000h

00BFFFh

008000h

007FFFh

004000h

000000h

003FFFh

PAGE 0 - 16 Kbytes

PAGE 1 - 16 Kbytes

PAGE 2 - 16 Kbytes

PAGE 3 - 16 Kbytes

SEGMENT 20h

64 Kbytes

200000h

21FFFFh

20C000h

20BFFFh

208000h
207FFFh

204000h

203FFFh

PAGE 80 - 16 Kbytes

PAGE 81 - 16 Kbytes

PAGE 82 - 16 Kbytes

PAGE 83 - 16 Kbytes

20FF 00h

20FFFFh

RAM

256 bytes

Internal

Reserved

SEGMENT 21h

64 Kbytes

20FFFFh

220000h

22FFFFh

210000h

SEGMENT 22h

64 Kbytes

228000h

229FFFh

max. 8 Kbytes

TDSRAM

Internal ROM

PAGE 88 - 16 Kbytes

PAGE 89 - 16 Kbytes

PAGE 90 - 16 Kbytes

PAGE 91 - 16 Kbytes

22C000h

22BFFFh

228000h

227FFFh

224000h

223FFFh

Reserved

max. 64 Kbytes

13/22

ST92195B - ELECTRICAL CHARACTERISTICS

2 ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Note: Stress above those listed as "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliabili ty.

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Value

Unit

Supply Voltage

- 0.3 to V

+ 7.0

SSA

Analog Ground

- 0.3 to V

+ 0.3

DDA

Analog Supply Voltage

-0.3 to V

+0.3

Input Voltage

- 0.3 to V

+0.3

Analog Input Voltage (A/D Converter)

- 0.3 to V

+0.3

SSA

- 0.3 to V

DDA

+0.3

Output Voltage

- 0.3 to V

+ 0.3

STG

Storage Temperature

- 55 to + 150

INJ

Pin Injected Current

Maximum Accumulated Pin

Injected Current In Device

- 5 to + 5

- 50 to +5 0

Symbol

Parameter

Value

Unit

Min.

Max.

Operating Temperature

Supply Voltage

4.5

5.5

DDA

Analog Supply Voltage (PLL)

4.5

5.5

OSCE

External Oscillator Frequency

3.3

8.7

MHz

OSCI

Internal Clock Frequency (INTCLK)

MHz

14/22

ST92195B - ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS
(

= 5V +/-10%;

= 0 to 70

C; unless otherwise specified)

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Max.

IHCK

Clock In high level

External clock

0.7 V

ILCK

Clock in low level

External clock

0.3 V

Input high level

TTL

2.0

Input low level

TTL

0.8

Input high level

CMOS

0.8 V

Input low level

CMOS

0.2 V

IHRS

Reset in high level

0.7 V

ILRS

Reset in low level

0.3 V

HYRS

Reset in hysteresis

0.3

IHY

P2.(1:0) input hysteresis

0.9

IHVH

HSYNC/VSYNC input high level

0.7 V

ILVH

HSYNC/VSYNC input low level

0.3 V

HYHV

HSYNC/VSYNC input hysteresis

0.5

Output high level

Push-pull Ild=-0.8mA

-0.8

Output low level

Push-pull ld=+1.6mA

0.4

WPU

Weak pull-up current

bidir. state

= 3V

= 7V

350

LKIO

I/O pin input leakage current

0<V

-10

+10

LKRS

Reset pin input

0<V

-10

+10

LKAD

A/D pin input leakage current

alternate funct. op. drain

-10

+10

LKOS

OSCIN pin input leakage current

0<V

-10

+10

15/22

ST92195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

PIN CAPACITANCE
(

= 5V +/-10%;

= 0 to 70

C; unless otherwise specified))

CURRENT CONSUMPTION

(

= 5V +/-10%;

= 0 to 70

C; unless otherwise specified)

Notes:
1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.

The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.

2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to

, HSYNC is driven by a 15625Hz clock.

All peripherals working including Display.

3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to

, HSYNC is driven by a 15625Hz clock.

The TDSRAM interface and the Slicers are working; the Display controller is not working.

4. VSYN C and HSYNC tied to

. External CLOCK pin (OSCIN) is hold low. All peripherals are disabled.

EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)
(

= 5V +/-10%;

= 0 to 70

C; unless otherwise specified))

TpC is the INTCLK clock period.

Symbol

Parameter

Conditions

Value

Unit

min

max

Pin Capacitance Digital Input/Output

Symbol

Parameter

Condition s

Value

Unit

min

typ.

max

DD1

Run Mode Current

notes 1,2; all On

100

DDA1

Run Mode Analog Current
(pin V

DDA

)

Timing Controller On

DD2

HALT Mode Current

notes 1,4

100

DDA2

HALT Mode Analog Current

(pin V

DDA

)

notes 1,4

100

Symbol

Parameter

Conditions

Value

Unit

INTCLK=24 MHz.

min

max

wLR

low level pulse width

TpC+12

wHR

high level pulse width

TpC+12

16/22

ST92195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS (Cont'd)

SPI TIMING TABLE
(

= 5V +/-10%;

= 0 to 70

C; Cload= 50pF)

(1) TpC is the OSCIN clock period; TpMC is the "Main Clock Frequency" period.

SKEW CORRECTOR TIMING TABLE
(

= 5V +/-10%,

= 0 to 70

C, unless otherwise specified)

(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope
of 100 fields

Symbol

Parameter

Conditi on

Value

Unit

min

max

sDI

Input Data Set-up Time

tbd

hDI

Input Data Hold Time

(1)

OSCIN/2 as internal Clock

1INTCLK

+100ns

dOV

SCK to Output Data Valid

tbd

hDO

Output Data Hold Time

tbd

wSKL

SCK Low Pulse Width

tbd

wSKH

SCK High Pulse Width

tbd

Symbol

Parameter

Conditions

max

Value

Unit

jskw

Jitter on RGB output

36 MHz Skew corrector clock frequency

17/22

ST92195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS (Cont'd)

OSD DAC CHARACTERISTICS (ROM DEVICES ONLY)
(

= 5V +/-10%,

= 0 to 70

C, unless otherwise specified).

OSD DAC CHARACTERISTICS (EPROM AND OTP DEVICES ONLY)
(

= 5V +/-10%,

= 0 to 70

C, unless otherwise specified).

Symbol

Parameter

Conditio ns

Value

Unit

min

typical

max

Output impedance: FB,R,G,B

300

500

700

Ohm

Output voltage: FB,R,G,B

Cload= 20pF

RL = 100K

code= 111

1.000

1.250

code= 011

0.450

0.500

code= 000

0.025

0.080

FB= 1

2.4

2.7

3.4

FB= 0

0.025

0.080

Global voltage accuracy

+/-5

Symbol

Parameter

Conditions

Value

Unit

min

typical

max

Output impedance: FB,R,G,B

300

500

700

Ohm

Output voltage: FB,R,G,B

Cload= 20pF

RL = 100K

code= 111

1.100

1.400

code= 011

0.600

0.800

code= 000

0.200

0.350

FB= 1

-0.8

FB= 0

0.400

Global voltage accuracy

+/-5

18/22

ST92195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS (Cont'd)

A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE
(

= 5V +/-10%;

= 0 to 70

C; unless otherwise specified

A/D CONVERTER. ANALOG PARAMETERS TABLE
(

= 5V +/-10%;

= 0 to 70

C; unless otherwise specified))

Notes: (*)

The values are expected at 25 Celsius degrees with

= 5V

(**)

'LSBs' , as used here, as a value of

/256

(1)

@ 24 MHz external clock

(2)

including Sample time

(3)

it must be considered as the on-chip series resistance before the sampling capacitor

(4)

DNL ERROR= max {[V(i) -V(i-1)] / LSB-1}

INL ERROR= max {[V(i) -V(0)] / LSB-i}

ABSOLUTE ACCUR ACY= overall max conversion error

Symbol

Parameter

OSCIN divide by

2;min/max

OSCIN divide

by 1; min/max

Value

Unit

min

max

low

Pulse Width

1.5

INTCLK

high

Pulse Distance

ext

Period/fast Mode

78+1

INTCLK

str

Start Conversion Delay

0.5

1.5

INTCLK

Core Clock issued by Timing Controller

low

Pulse Width

high

Pulse Distance

ext

Period/fast Mode

str

Start Conversion Delay

Parameter

Value

Unit

Note

typ (*)

min

max

(**)

Analog Input Range

Conversion Time Fast/Slow

78/138

INTCLK

(1,2)

Sample Time Fast/Slow

51.5/87.5

INTCLK

(1)

Power-up Time

Resolution

bits

Differential Non Linearity

1.5

2.5

LSBs

(4)

Integral Non Linearity

LSBs

(4)

Absolute Accuracy

LSBs

(4)

Input Resistance

1.5

Kohm

(3)

Hold Capacitance

1.92

19/22

ST92195B - GENERAL INFORMATION

3 GENERAL INFORMATION

3.1 PACKAGE MECHANICAL DATA

Figure 7. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width

Figure 8. 64-Pin Thin Quad Flat Package

Dim.

inches

Min

Typ

Max

Min

Typ

Max

6.35

0.250

0.38

0.015

3.18

4.95 0.125

0.195

0.41

0.016

0.89

0.035

0.20

0.38 0.008

0.015

50.29

53.21 1.980

2.095

15.01

0.591

12.32

14.73 0.485

0.580

1.78

0.070

15.24

0.600

17.78

0.700

2.92

5.08 0.115

0.200

Number of Pins

PDIP56S

Dim

inches

Min

Typ

Max

Min

Typ

Max

1.60

0.063

0.05

0.15 0.002

0.006

1.35 1.40 1.45 0.053 0.055 0.057

0.30 0.37 0.45 0.012 0.015 0.018

0.09

0.20 0.004

0.008

16.00

0.630

14.00

0.551

12.00

0.472

16.00

0.630

14.00

0.551

12.00

0.472

0.80

0.031

3.5

0.45 0.60 0.75 0.018 0.024 0.030

1.00

0.039

Number of Pins

20/22

ST92195B - GENERAL INFORMATION

PACKAGE MECHANICAL DATA (Cont'd)

Figure 9. 56-Pin Shrink Ceramic Dual In Line Package, 600-mil Width

Figure 10. 64-Pin Ceramic Quad Flat Package

Dim.

inches

Min

Typ

Max

Min

Typ

Max

4.17

0.164

0.76

0.030

0.38

0.46

0.56 0.015 0.018 0.022

0.76

0.89

1.02 0.030 0.035 0.040

0.23

0.25

0.38 0.009 0.010 0.015

50.04 50.80 51.56 1.970 2.000 2.030

48.01

1.890

14.48 14.99 15.49 0.570 0.590 0.610

1.78

0.070

14.12 14.38 14.63 0.556 0.566 0.576

18.69 18.95 19.20 0.736 0.746 0.756

1.14

0.045

11.05 11.30 11.56 0.435 0.445 0.455

15.11 15.37 15.62 0.595 0.605 0.615

2.92

5.08 0.115

0.200

1.40

0.055

Number of Pins

CDIP56SW

Dim

inches

Min

Typ

Max

Min

Typ

Max

3.27

0.129

0.50

0.020

0.30 0.35 0.45 0.012 0.014 0.018

0.13 0.15 0.23 0.005 0.006 0.009

16.65 17.20 17.75 0.656 0.677 0.699

13.57 13.97 14.37 0.534 0.550 0.566

12.00

0.472

0.80

0.031

12.70

0.500

0.96

0.038

0.35 0.80

0.014 0.031

8.31

0.327

Number of Pins

CQFP064W

21/22

ST92195B - GENERAL INFORMATION

3.2 ORDERING INFORMATION

Each device is available for production in a user
programmable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. The common EPROM versions for de-
bugging and prototyping features the maximum
memory size and peripherals of the family. Care
must be taken to only use resources available on
the target device.

3.2.1 Transfer Of Customer Code

Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.

Figure 11. ROM Factory Coded Device Types

Figure 12. OTP User Programmable Device Types

Figure 13. EPROM User Programmable Device Types

DEVICE PACKAGE

TEMP.

RANGE

XXX

Code name (defined by STMicroelectronics)

1= standard 0 to +70

B= Plastic DIP56
T= Plastic TQFP64

ST92195B1
ST92195B2
ST92195B3
ST92195B4
ST92195B5
ST92195B6
ST92195B7

DEVICE PACKAGE

TEMP.

RANGE

Code name (defined by STMicroelectronics)

1= 0 to +70

B= Plastic DIP56
T= Plastic TQFP64

ST92T195B7

XXX

DEVICE PACKAGE

TEMP.

RANGE

0= 25

B= Ceramic DIP 56 pin
T= Ceramic QFP 64 pin

ST92E195B7

22/22

ST92195B - GENERAL INFORMATION

Notes:

Information furnished is believed to be accurate and reliable. However, STMi croelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as criti cal components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I

C Components by STMicroelectronics conveys a license under the Philips I

C Patent. Rights to use these components in an

C system is granted provided that the system conforms to the I

C Standard Specification as defined by Philips.

STMi croelectronics Group of Companies

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Sweden - Switzerland - United Kingdom - U.S.A.

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