1/23
May 2003
M27W032
32 Mbit (2Mb x16) 3V Supply FlexibleROMTM Memory
FEATURES SUMMARY
s
ONE TIME PROGRAMMABLE
s
SUPPLY VOLTAGE
V
CC
=
2.7 to 3.6V for Read
V
PP
=
11.4 to 12.6V for Program
s
ACCESS TIME
90ns at V
CC
=
3.0 to 3.6V
100, 110ns at V
CC
=
2.7 to 3.6V
s
PROGRAMMING TIME
9s per Word typical
Multiple Word Programming Option
(4s typical Chip Program)
s
SUITABLE FOR ON-BOARD PROGRAMMING
s
PROGRAM CONTROLLER
Embedded Word Program algorithms
s
ELECTRONIC SIGNATURE
Manufacturer Code: 0020h
Device Code : 888Eh
Figure 1. Packages
TSOP48 (N)
12 x 20mm
SO44 (M)
M27W032
2/23
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
CC
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
PP
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Setup Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Program Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/23
M27W032
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
PP
Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Chip Enable Controlled, Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . . . . . . . . . 19
SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data . . . . . . . . . 19
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . . . . . . . . 20
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . . . . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M27W032
4/23
SUMMARY DESCRIPTION
The M27W032 is a 32 Mbit (2Mb x16) non-volatile,
One Time Programmable (OTP), FlexibleROMTM
Memory. Read operations can be performed using
a single low voltage (2.7 to 3.6V) supply. Program
operations require an additional V
PP
(11.4 to
12.6V) power supply. On power-up the memory
defaults to Read mode where it can be read in the
same way as a ROM or EPROM.
Program commands are written to the Command
Interface of the memory. An on-chip Program Con-
troller (PC) simplifies the process of programming
the memory by taking care of all of the special op-
erations that are required to update the memory
contents.
The M27W032 features an innovative command,
Multiple Word Program, used to program large
streams of data. It greatly reduces the total pro-
gramming time when a large number of Words are
written to the memory at any one time. Using this
command the entire memory can be programmed
in 4s, compared to 18s using the standard Word
Program.
The end of a program operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Chip Enable and Output Enable signals control the
bus operation of the memory. They allow simple
connection to most microprocessors, often without
additional logic.
The memory is offered in SO44 and TSOP48 (12
x 20mm) packages. The memory is supplied with
all the bits set to '1'.
Figure 2. Logic Diagram
Table 1. Signal Names
AI05928
21
A0-A20
DQ0-DQ15
VCC
M27W032
E
VSS
16
G
VPP
A0-A20
Address Inputs
DQ0-DQ15
Data Inputs/Outputs
E
Chip Enable
G
Output Enable
V
CC
Supply Voltage read
V
PP
Supply Voltage program
V
SS
Ground
NC
Not Connected Internally
5/23
M27W032
Figure 3. SO Connections
Figure 4. TSOP Connections
G
DQ0
DQ8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
DQ7
A12
A16
DQ15
DQ5
DQ2
DQ3
VCC
DQ11
DQ4
DQ14
A9
A19
NC
A4
A7
AI05926
M27W032
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
20
19
18
17
DQ1
DQ9
A6
A5
DQ6
DQ13
44
39
38
37
36
35
34
33
A11
A10
DQ10
21
DQ12
40
43
1
42
41
A17
A8
A18
A20
VPP
DQ3
DQ9
DQ2
A6
DQ0
A3
DQ6
A8
A9
DQ13
A17
A10
DQ14
A2
DQ12
DQ10
DQ15
DQ4
DQ5
A7
DQ7
AI05927
M27W032
12
1
13
24
25
36
37
48
DQ8
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
A15
A14
VSS
E
A0
NC
VPP
VSS
VCC
VSS
A20
VSS
VCC
VSS
M27W032
6/23
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program Controller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the command
sent to the Command Interface of the Program
Controller. When reading the Status Register they
report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Interface does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write opera-
tions, when V
PP
is in the V
HH
range.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operations of the memory. It
also allows Bus Write operations, when V
PP
is in
the V
HH
range.
V
CC
Supply Voltage. The V
CC
Supply Voltage
supplies the power for Read operations.
A 0.1F capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program opera-
tions, I
CC3
.
V
PP
Program Supply Voltage. V
PP
is both a
power supply and Write Protect pin. The two func-
tions are selected by the voltage range applied to
the pin.
When the V
PP
is in the V
HH
range (see Table 10,
DC Characteristic, for the relevant values) the Pro-
gram operation is enabled. During such opera-
tions the V
PP
must be stable in the V
HH
range.
If the V
PP
is kept under the V
HH
range, particularly
in the voltage range 0 to 3.6V, any Program oper-
ation is disabled or stopped.
Note that V
PP
must not be left floating or uncon-
nected as the device may become unreliable.
Vss Ground. The V
SS
Ground is the reference
for all voltage measurements.
7/23
M27W032
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 2, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs and applying a Low signal, V
IL
, to Chip En-
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 10, Read AC
Waveforms, and Table 11, Read AC Characteris-
tics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
when V
PP
is set to V
HH
. A valid Bus Write opera-
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, V
IH
,
during the whole Bus Write operation. See Figure
11, Write AC Waveforms, and Table 12, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby. When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within V
CC
0.2V. For the Standby current
level see Table 10, DC Characteristics.
During program operation the memory will contin-
ue to use the Program Supply Current, I
CC3
, for
Program operation until the operation completes.
Automatic Standby. If CMOS levels (V
CC
0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2, Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Table 2. Bus Operations
Note: 1. X = V
IL
or V
IH
.
2. XX = V
IL
, V
IH
or V
HH
3. When reading Status Register during Program algorithm execution V
PP
must be kept at V
HH
.
Operation
E
G
V
PP
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15-DQ0
Bus Read
V
IL
V
IL
XX
(3)
Cell Address
Data Output
Bus Write
V
IL
V
IH
V
HH
Command Address
Data Input
Output Disable
X
V
IH
X
X
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
HH
A0 = V
IL
, A1 = V
IL
,
Others V
IL
or V
IH
0020h
Read Device Code
V
IL
V
IL
V
HH
A0 = V
IH
, A1 = V
IL
,
Others V
IL
or V
IH
888Eh
M27W032
8/23
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 3 and 4, for a summary of the com-
mands.
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
V
PP
must be set to V
HH
during the Read/Reset
command. If V
PP
is set to either V
IL
or V
IH
the com-
mand will be ignored. The command can be is-
sued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
Auto Select Command.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. V
PP
must be set to V
HH
during the Auto Select com-
mand. If V
PP
is set to either V
IL
or V
IH
the com-
mand will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Se-
lect command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
IL
and A1 = V
IL
. The other address bits
may be set to either V
IL
or V
IH
.
The Device Code can be read using a Bus Read
operation with A0 = V
IH
and A1 = V
IL
. The other
address bits may be set to either V
IL
or V
IH
.
Word Program Command.
The Word Program command can be used to pro-
gram a Word to the memory array. V
PP
must be
set to V
HH
during Word Program. If V
PP
is set to ei-
ther V
IL
or V
IH
the command will be ignored, the
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the PC.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 5. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at '0' back to '1'.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
once. V
PP
must be set to V
HH
during Multiple Word
Program. If V
PP
is set either V
IL
or V
IH
the com-
mand will be ignored, the data will remain un-
changed and the device will revert to Read mode.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the PC has started (see Table 6 and
Figure 6).
Program Phase. The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (re-
fer to Table 4, Multiple Word Program and Figure
5, Multiple Word Program Flowchart).
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the PC is ready to accept the opera-
tion (see Table 6 and Figure 6).
The Program Phase is executed in three different
sub-phases:
1. The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
Start Address and the first Word to be
programmed.
2. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A20 equal to the
9/23
M27W032
Start Address), that indicates to the PC that the
Program Phase has to continue. A0 to A16 are
`don't care'.
3. Finally, after all Words have been programmed,
a Bus Write operation (the (n+1)
th
) with a Final
Address, FA (A17 or a higher address pin
different from the Start Address), ends the
Program Phase.
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the PC is ready for the next operation
or if the reprogram of the location has failed (see
Table 6 and Figure 6).
Three successive steps are required to execute
the Verify Phase of the command:
1. The first Bus Write operation of the Verify Phase
latches the Start Address and the Word to be
verified.
2. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
but only a Continue Address, CA (A17 to A20
equal to the Start Address).
3. Finally, after all Words have been verified, a Bus
Write cycle with a Final Address, FA (A17 or a
higher address pin different from the Start
Address) ends the Verify Phase.
Exit Phase. After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 6
and Figure 6).
If the Verify Phase is successful, the memory re-
turns to Read mode and DQ6 stops toggling.
If the PC fails to reprogram a given location, the
Verify Phase terminates, DQ6 continues toggling
and error bit DQ5 is set in the Status Register. If
the error is due to a V
PP
failure DQ4 is also set.
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 5.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
Note that the Multiple Word Program command
cannot change a bit set to '0' back to '1'.
M27W032
10/23
Table 3. Standard Commands
Note: X Don't Care, PA Program Address, PD Program Data. All values in the table are in hexadecimal. The Command Interface only uses
A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ15 are Don't Care.
Table 4. Multiple Word Program Command
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don't
Care, n = number of Words to be programmed.
Table 5. Program Times
Note: 1. T
A
= 25C, V
PP
= 12V.
Command
Leng
th
Bus Write Operations
1st
2nd
3rd
4th
Add
Data
Add
Data
Add
Data
Add
Data
Read/Reset
1
X
F0
3
555
AA
2AA
55
X
F0
Auto Select
3
555
AA
2AA
55
555
90
Word Program
4
555
AA
2AA
55
555
A0
PA
PD
Phase
Le
ngth
Bus Write Operations
1st
2nd
3rd
4th
5th
nth
Final
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Set-Up 3
555
AA
2AA
55
555
20
Program n+1
SA
PD1
CA
PD2
CA
PD3
CA
PD4
CA
PD5
CA
PAn
FA
X
Verify
n+1
SA
PD1
CA
PD2
CA
PD3
CA
PD4
CA
PD5
CA
PAn
FA
X
Parameter
Typ
(1)
Max
Unit
Program (Word)
9
200
s
Chip Program (Multiple Word)
4
70
s
Chip Program (Word by Word)
18
70
s
11/23
M27W032
Figure 5. Multiple Word Program Flowchart
Write AAh
Address 555h
AI05954b
Start
Read Status
Register
YES
NO
DQ0 = 0?
Write 55h
Address 2AAh
Write 20h
Address 555h
Write Data1
Start Address
Write Data 2
Continue Address
YES
NO
Read Status
Register
Write Data n
Continue Address
YES
NO
Read Status
Register
Write XX
Final Address
Read Status
Register
NO
Write Data1
Start Address
Write Data 2
Continue Address
NO
Read Status
Register
Write Data n
Continue Address
Read Status
Register
Write XX
Final Address
YES
Write F0h
Address XX
Exit (read mode)
DQ0 = 0?
DQ0 = 0?
DQ0 = 0?
DQ0 = 0?
DQ0 = 0?
Read Status
Register
NO
DQ6
toggling?
DQ4 = 0?
YES
Fail, V
PP
error
NO
Program
Phase
YES
NO
DQ0 = 0?
YES
Setup time
exceeded?
EXIT (
setup failed
)
NO
DQ0 = 0?
Read Status
Register
NO
YES
YES
NO
DQ5 = 1?
YES
NO
DQ5 = 1?
YES
DQ6
toggling?
Read Status
Register
NO
YES
YES
NO
Fail error
YES
NO
Setup
Phase
Verify
Phase
Exit
Phase
Read Status
Register
DQ5 = 1 ?
M27W032
12/23
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program opera-
tions. The bits in the Status Register are summa-
rized in Table 6, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program Controller
has successfully completed its operation. The
Data Polling Bit is output on DQ7 when the Status
Register is read.
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement.
Figure 6, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program Controller has suc-
cessfully completed its operation. The Toggle Bit
is output on DQ6 when the Status Register is read.
During Program operations the Toggle Bit chang-
es from '0' to '1' to '0', etc., with successive Bus
Read operations at any address. After successful
completion of the operation the memory returns to
Read mode.
Figure 7, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program Controller.
The Error Bit is set to '1' when a Program opera-
tion fails to write the correct data to the memory. If
the Error Bit is set a Read/Reset command must
be issued before other commands are issued. The
Error bit is output on DQ5 when the Status Regis-
ter is read.
Note that the Program command cannot change a
bit set to '0' back to '1' and attempting to do so will
set DQ5 to `1'. A Bus Read operation to that ad-
dress will show the bit is still `0'.
V
PP
Status Bit (DQ4). The V
PP
Status Bit can be
used to identify if any Program operation has failed
due to a V
PP
error. If V
PP
falls below V
HH
during
any Program operation, the operation aborts and
DQ4 is set to `1'. If V
PP
remains at V
HH
throughout
the Program operation, the operation completes
and DQ4 is set to `0'.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the Program Controller is active or inactive during
Multiple Word Program. When the Program Con-
troller has written one Word and is ready to accept
the next Word, the bit is set to `0'.
Status Register Bit DQ1 is reserved.
13/23
M27W032
Table 6. Status Register Bits
Note: 1. Unspecified data bits should be ignored.
2. DQ4 = 0 if V
PP
V
HH
during Program algorithm execution; DQ4 = 1 if V
PP
< V
HH
during Program algorithm execution.
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
Command
(1)
P.C. Status
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
Multiple Word Program
Programming
Toggle
0
0
1
Waiting for data
Toggle
0
0
0
Program fail
Toggle
1
(2)
0
1
Word Program
Programming
DQ7
Toggle
0
0
Program error
DQ7
Toggle
1
(2)
0
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL
PASS
AI03598
DQ7
=
DATA
YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA
YES
NO
READ DQ6
START
READ DQ6
TWICE
FAIL
PASS
AI01370B
DQ6
=
TOGGLE
NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
M27W032
14/23
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
Note: 1. Minimum voltage may undershoot to 2V for less than 20ns during transitions.
2. Maximum voltage may overshoot to V
CC
+2V for less than 20ns during transitions.
3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. V
PP
must not remain at V
HH
for more than a total
of 80hrs.
Symbol
Parameter
Min
Max
Unit
T
BIAS
Temperature Under Bias
50
125
C
T
STG
Storage Temperature
65
150
C
V
IO
Input or Output Voltage
(1,2)
0.6
V
CC
+0.6
V
V
CC
Read Supply Voltage
0.6
4
V
V
PP
Program Supply Voltage
(3)
0.6
13.5
V
15/23
M27W032
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 8, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 8. Operating and AC Measurement Conditions
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
Table 9. Device Capacitance
Note: Sampled only, not 100% tested.
Parameter
M27W032
Unit
100, 110
Min
Max
V
CC
Read Supply Voltage
2.7
3.6
V
V
PP
Program Supply Voltage
11.4
12.6
V
Ambient Operating Temperature
0
70
C
Load Capacitance (C
L
)
30
pF
Input Rise and Fall Times
10
ns
Input Pulse Voltages
0 to 3
V
Input and Output Timing Ref. Voltages
1.5
V
AI05546
3V
0V
1.5V
AI05447
1.3V
OUT
CL
CL = 30pF
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
M27W032
16/23
Table 10. DC Characteristics
Note: 1. V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
2. Average Value.
Symbol
Parameter
(1)
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
1
A
I
CC1
Supply Current (Read)
E = V
IL
, G = V
IH
,
I
OUT
= 0mA, f = 6MHz
10
mA
I
CC2
(2)
Supply Current (Standby)
E = V
CC
0.2V
100
A
I
CC3
Supply Current (Program)
PC active
20
mA
V
IL
Input Low Voltage
0.5
0.8
V
V
IH
Input High Voltage
0.7V
CC
V
CC
+0.3
V
V
OL
Output Low Voltage
I
OL
= 1.8mA
0.45
V
V
OH
Output High Voltage
I
OH
= 100
A
V
CC
0.4
V
V
HH
V
PP
Program Voltage
11.4
12.6
V
I
HH
V
PP
Current (Program)
PC Active
10
mA
17/23
M27W032
Figure 10. Read AC Waveforms
Table 11. Read AC Characteristics
Note: 1. V
PP
must be applied after V
CC
and with the Chip Enable (E) at V
IH
.
2. Sampled only, not 100% tested.
Symbol
Alt
Parameter
(1)
Test Condition
M27W032
Unit
100
110
V
CC
= 3.0 to 3.6V V
CC
= 2.7 to 3.6V V
CC
= 2.7 to 3.6V
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
,
G = V
IL
Max
90
100
110
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
Max
90
100
110
ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E = V
IL
Max
35
35
35
ns
t
EHQZ
(2)
t
HZ
Chip Enable High to
Output Hi-Z
G = V
IL
Max
30
30
30
ns
t
GHQZ
(2)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
Max
30
30
30
ns
t
AXQX
t
OH
Address Transition to
Output Transition
Min
0
0
0
ns
AI05929
tAVQV
tAXQX
tEHQZ
tGLQV
VALID
A0-A20
G
DQ0-DQ15
E
tELQV
tGHQZ
VALID
M27W032
18/23
Figure 11. Chip Enable Controlled, Write AC Waveforms
Table 12. Chip Enable Controlled, Write AC Characteristics
Note: 1. T
A
= 25C; V
PP
= 11.4 to 12.6V. V
CC
= 2.7 to 3.6V.
V
PP
must be applied after V
CC
and with the Chip Enable (E) at V
IH
.
Sampled only, not 100% tested.
2. Not required in Auto Select or Read/Reset command sequences.
Symbol
Alt
Parameter
(1)
M27W032
Unit
t
ELEH
t
CP
Chip Enable Low to Chip Enable High
Min
50
ns
t
DVEH
t
DS
Input Valid to Chip Enable High
Min
50
ns
t
EHDX
t
DH
Chip Enable High to Input Transition
Min
0
ns
t
EHEL
t
CPH
Chip Enable High to Chip Enable Low
Min
50
ns
t
AVEL
t
AS
Address Valid to Chip Enable Low
Min
0
ns
t
ELAX
t
AH
Chip Enable Low to Address Transition
Min
100
ns
t
GHEL
Output Enable High Chip Enable Low
Min
10
ns
t
EHGL
t
OEH
Chip Enable High to Output Enable Low
Min
10
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
Min
50
s
t
VPHEL
(2)
t
VCS
V
PP
High to Chip Enable Low
Min
500
ns
AI05930
E
G
A0-A20
DQ0-DQ15
VALID
VALID
VCC
tVCHEL
tEHEL
tAVEL
tEHGL
tELAX
tEHDX
tDVEH
tELEH
tGHEL
VPP
tVPHEL
19/23
M27W032
PACKAGE MECHANICAL
Figure 12. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline
Note: Drawing is not to scale.
Table 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data
Symbol
millimeters
inches
Typ
Min
Max
Typ
Min
Max
A
3.00
0.118
A1
0.10
0.004
A2
2.69
2.56
2.79
0.106
0.101
0.110
b
0.35
0.50
0.014
0.020
c
0.18
0.28
0.007
0.011
D
28.50
28.37
28.63
1.122
1.117
1.127
ddd
0.10
0.004
E
16.03
15.77
16.28
0.631
0.621
0.641
E1
12.60
12.47
12.73
0.496
0.491
0.501
e
1.27
0.050
L
0.79
0.031
L1
1.73
0.068
8
8
N
44
44
E1
44
e
D
c
E
1
22
23
b
SO-F
L
A1
A
ddd
A2
L1
M27W032
20/23
Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Note: Drawing is not to scale.
Table 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol
millimeters
inches
Typ
Min
Max
Typ
Min
Max
A
1.20
0.0472
A1
0.05
0.15
0.0020
0.0059
A2
0.95
1.05
0.0374
0.0413
B
0.17
0.27
0.0067
0.0106
C
0.10
0.21
0.0039
0.0083
CP
0.10
0.0039
D
19.80
20.20
0.7795
0.7953
D1
18.30
18.50
0.7205
0.7283
E
11.90
12.10
0.4685
0.4764
e
0.50
0.0197
L
0.50
0.70
0.0197
0.0276
0
5
0
5
N
48
48
TSOP-a
D1
E
1
N
CP
B
e
A2
A
N/2
D
DIE
C
L
A1
21/23
M27W032
PART NUMBERING
Table 15. Ordering Information Scheme
Note: 1. This speed also guarantees 90ns access time at V
CC
= 3.0 to 3.6V.
Devices are shipped from the factory with all the bits set to '1'.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Example:
M27W032
100 N
1
T
Device Type
M27 = FlexibleROM
TM
Memory
Operating Voltage
W = V
CC
= 2.7 to 3.6V
Device Function
032 = 32 Mbit (x16)
Speed
100 = 100 ns
(1)
110 = 110 ns
Package
M = SO44, 500mils body width
N = TSOP48: 12 x 20 mm
Temperature Range
1 = 0 to 70 C
Option
T = Tape & Reel Packing
M27W032
22/23
REVISION HISTORY
Table 16. Document Revision History
Date
Version
Revision Details
28-Jun-2002
1.0
First Issue
09-Jul-2002
2.0
100ns speed class added (90ns at V
CC
= 3.0 to 3.6V)
Product Name changed
02-Aug-2002
2.1
Multiple Word Program Command Table clarified (Table 4)
I
CC1
, I
CC2
clarified (Table 10)
27-Sep-2002
2.2
Product Naming revised
28-Nov-2002
2.3
OTP specification added
SO44 package changed to 500mils body width
Bus Operation table clarified (Table 2)
Read/Reset, Auto Select and Multiple Word Program commands clarified
90ns speed class obtained from the 100ns at V
CC
= 3.0 to 3.6V - clarification (Table 11
and 12)
19-Dec-2002
2.4
Document maturity changed to Preliminary Data
21-Jan-2003
2.5
TSOP Connections diagram updated (Figure 4)
20-Feb-2003
2.6
TSOP Connections diagram changed back as in version 2.4 (Figure 4)
09-May-2003
2.7
Document maturity changed to Data Sheet
23/23
M27W032
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
FlexibleROM is a pending trademark of STMicroelectronics
All other names are the property of their respective owners
2003 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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