1/25
L6563
November 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
MAIN FEATURES
TRANSITION-MODE CONTROL OF PFC PRE-
REGULATORS
VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLTAGE PROTECTION
TRACKING BOOST FUNCTION
PROTECTION AGAINST FEEDBACK LOOP
FAILURE (LATCHED SHUTDOWN)
INTERFACE FOR CASCADED CONVER-
TER'S PWM CONTROLLER
INPUT VOLTAGE FEEDFORWARD (1/V
2
)
REMOTE ON/OFF CONTROL
LOW (
90A) START-UP CURRENT
5 mA MAX. QUIESCENT CURRENT
1.5% (@ Tj = 25C) INTERNAL REFERENCE
VOLTAGE
-600/+800 mA TOTEM POLE GATE DRIVER
WITH ACTIVE PULL-DOWN DURING UVLO
SO14 PACKAGE
1.1 APPLICATIONS
PFC PRE-REGULATORS FOR:
HI-END AC-DC ADAPTER/CHARGER
DESKTOP PC, SERVER, WEB SERVER
IEC61000-3-2 OR JEIDA-MITI COMPLIANT
SMPS, IN EXCESS OF 250W
2
DESCRIPTION
The device is a current-mode PFC controller oper-
ating in Transition Mode (TM). Based on the core
of a standard TM PFC controller, it offers improved
performance and additional functions.
PRELIMINARY DATA
ADVANCED TRANSITION-MODE PFC CONTROLLER
Figure 2. Block Diagram
+
-
V
REF2
Vbias
(INTERNAL SUPPLY BUS)
+
-
2.5V
R1
R2
+
-
-
+
ZERO CURRENT
DETECTOR
V
CC
14
1
2
3
4
ZCD
V
CC
INV
COMP
MULT
CS
GD
13
11
GND
12
MULTIPLIER
R
S
Q
STARTER
1.7V
+
-
6
TBO
+
-
2.5V
PFC_OK
7
1:1
CURRENT
MIRROR
+
-
RU N
10
0.52V
0.62V
PW M_LATCH
8
5
VFF
LEADING-EDGE
BLANKING
1:1
BUFFER
from
VFF
1.4V
0.7V
PW M_STOP
9
Vbias
UVLO
COMPARA TOR
+
-
0.2V
0.3V
15 V
SAT
DISABLE
LATCH
UVLO
3V
SAT
Ideal diode
1 / V
2
Starter
OFF
Driver
Q
TRACKING
BOOST
ON/OFF CONTROL
(BROWNOUT DETECTION)
LINE VOLTAGE
FEEDFORWARD
INDUCTOR
SATURATION
DETECTION
FEEDBACK
FAILUR E
DETECTION
VOLTAGE
REGULATOR
Voltage
references
Rev. 1
Figure 1. Package
Table 1. Order Codes
Part Number
Package
L6563
SO14
L6563TR
SO14 in Tape & Reel
SO14
L6563
2/25
2 DESCRIPTION (continued)
The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the
mains current, allows wide-range-mains operation with an extremely low THD even over a large load
range.
The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @T
j
= 25C)
internal voltage reference. The stability of the loop and the transient response to sudden mains voltage
changes are improved by the voltage feedforward function (1/V
2
correction).
Additionally, the IC provides the option for tracking boost operation (where the output voltage is changed
tracking the mains voltage). The device features extremely low consumption (
90 A before start-up and
5 mA running).
An interface with the PWM controller of the DC-DC converter supplied by the PFC pre-regulator is provid-
ed: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage
(feedback loop failure, boost inductor's core saturation) and to disable the PFC stage in case of light load
for the DC-DC converter, so as to make it easier to comply with energy saving norms (Blue Angel, Ener-
gyStar, Energy2000, etc.). The device includes disable functions suitable for remote ON/OFF control both
in systems where the PFC pre-regulator works as a master and in those where it works as a slave.
In addition to an effective two-step OVP that handles normal operation overvoltages, the IC provides also
a protection against feedback loop failures or erroneous output voltage setting.
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Figure 3. Pin Connection (Top view)
Symbol
Pin
Parameter
Value
Unit
Vcc
14
IC Supply voltage (Icc = 20 mA)
self-limited
V
---
2, 4 to 6, 8 to 10
Analog Inputs & Outputs
-0.3 to 8
V
---
1, 3, 7
Max. pin voltage (I
pin
=1 mA)
Self-limited
V
I
PWM_STOP
10
Max. sink current
3
mA
I
ZCD
11
Zero Current Detector Max. Current
-10 (source)
10 (sink)
mA
Ptot
Power Dissipation @Tamb = 50C
0.75
W
Tj
Junction Temperature Operating range
-25 to 150
C
Tstg
Storage Temperature
-55 to 150
C
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance, Junction-to-ambient
Max.
120
C/W
INV
COMP
MULT
CS
VFF
TBO
PFC_OK
Vcc
GD
GND
ZCD
RUN
PWM_STOP
PWM_LATCH
1
2
3
4
5
6
7
14
13
12
11
10
9
8
3/25
L6563
Table 4. Pin Description
Pin #
Pin Name
Function
1
INV
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
The pin normally features high impedance but, if the tracking boost function is used, an inter-
nal current generator programmed by TBO (pin #6) is activated. It sinks current from the pin
to change the output voltage so that it tracks the mains voltage.
2
COMP
Output of the error amplifier. A compensation network is placed between this pin and INV (pin
#1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
3
MULT
Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop. The voltage on this pin is
used also to derive the information on the RMS mains voltage.
4
CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resis-
tor, the resulting voltage is applied to this pin and compared with an internal reference to
determine MOSFET's turn-off.
A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor sat-
uration) and, on this occurrence, shuts down the IC, reduces its consumption almost to the
start-up level and asserts PWM_LATCH (pin #8) high.
5
VFF
Second input to the multiplier for 1/V
2
function. A capacitor and a parallel resistor must be
connected from the pin to GND. They complete the internal peak-holding circuit that derives
the information on the RMS mains voltage. The voltage at this pin, a DC level equal to the
peak voltage at pin MULT (#3), compensates the control loop gain dependence on the mains
voltage. Never connect the pin directly to GND.
6
TBO
Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected
between this pin and GND defines a current that is sunk from pin INV (#1). In this way, the
output voltage is changed proportionally to the mains voltage (tracking boost). If this function
is not used leave this pin open.
7
PFC_OK
PFC pre-regulator output voltage monitoring/disable function. This pin senses the output volt-
age of the PFC pre-regulator through a resistor divider and is used for protection purposes. If
the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes almost to the
start-up level and this condition is latched. PWM_LATCH pin is asserted high. Normal opera-
tion can be resumed only by cycling the Vcc. This function is used for protection in case the
feedback loop fails.
If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is
considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these
functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V.
8
PWM_LATCH
Output pin for fault signaling. During normal operation this pin features high impedance. If
either a voltage above 2.5V at PFC_OK (pin #7) or a voltage above 1.7V on CS (pin #4) is
detected the pin is asserted high. Normally, this pin is used to stop the operation of the DC-
DC converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM
controller. If not used, the pin will be left floating.
9
PWM_STOP
Output pin for fault signaling. During normal operation this pin features high impedance. If the
IC is disabled by a voltage below 0.5V on RUN (pin #10) the voltage at the pin is pulled to
ground. Normally, this pin is used to temporarily stop the operation of the DC-DC converter
supplied by the PFC pre-regulator by disabling its PWM controller. If not used, the pin will be
left floating.
10
RUN
Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and brings
its consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as
the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin #5) either directly or
through a resistor divider to use this function as brownout (AC mains undervoltage) protec-
tion, tie to INV (pin #1) if the function is not used.
11
ZCD
Boost inductor's demagnetization sensing input for transition-mode operation. A negative-
going edge triggers MOSFET's turn-on.
12
GND
Ground. Current return for both the signal part of the IC and the gate driver.
13
GD
Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's
with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
clamped at about 12V to avoid excessive gate voltages.
14
Vcc
Supply Voltage of both the signal part of the IC and the gate driver.
L6563
4/25
Figure 4. Typical System Block Diagram
Table 5. Electrical Characteristcs
(T
j
= -25 to 125C, V
cc
=12, C
o
= 1 nF between pin GD and GND, C
FF
=1F between pin V
FF
and GND;
unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE
Vcc
Operating range
After turn-on
10.3
22
V
Vcc
On
Turn-on threshold
(1)
11
12
13
V
Vcc
Off
Turn-off threshold
(1)
8.7
9.5
10.3
V
Hys
Hysteresis
2.3
2.7
V
V
Z
Zener Voltage
Icc = 20 mA
22
25
28
V
SUPPLY CURRENT
I
start-up
Start-up Current
Before turn-on, Vcc=10V
50
90
A
I
q
Quiescent Current
After turn-on
3
5
mA
I
CC
Operating Supply Current
@ 70 kHz
3.8
5.5
mA
I
qdis
Idle state quiescent Current
Latched by PFC_OK>Vthl or
Vcs>V
CSdis
180
250
A
Disabled by PFC_OK<Vth or
RUN<V
DIS
1.5
2.2
mA
I
q
Quiescent Current
During static/dynamic OVP
2
3
mA
MULTIPLIER INPUT
I
MULT
Input Bias Current
V
MULT
= 0 to 3 V
-0.2
-1
A
V
MULT
Linear Operation Range
0 to 3
V
V
CLAMP
Internal clamp level
I
MULT
= 1 mA
9
9.5
V
Output Max. Slope
V
MULT
=0 to 0.5V, V
FF
=0.8V
V
COMP
= Upper clamp
2.2
2.34
V/V
K
M
Gain (3)
V
MULT
= 1 V, V
COMP
= 4 V,
V
VFF
= V
MULT
0.375
0.45
0.525
1/V
V
inac
V
outdc
PWM is turned off in case of PFC's
anomalous operation for safety
PFC can be turned off at light
load to ease compliance with
energy saving regulations.
L6563
PWM or
Resonant
CONTROLLER
PFC PRE-REGULATOR
DC-DC CONVERTER
V
c s
V
MU L T
---------------------
5/25
L6563
ERROR AMPLIFIER
V
INV
Voltage Feedback Input
Threshold
T
j
= 25 C
2.465
2.5
2.535
V
10.3 V < Vcc < 22 V (2)
2.44
2.56
Line Regulation
Vcc = 10.3 V to 22V
2
5
mV
I
INV
Input Bias Current
TBO open, V
INV
= 0 to 4 V
-0.2
-1
A
V
INVCLAMP
Internal clamp level
I
INV
= 1 mA
9
9.5
V
Gv
Voltage Gain
Open loop
60
80
dB
GB
Gain-Bandwidth Product
1
MHz
I
COMP
Source Current
V
COMP
= 4V, V
INV
= 2.4 V
-2
-3.5
-5
mA
Sink Current
V
COMP
= 4V, V
INV
= 2.6 V
2.5
4.5
mA
V
COMP
Upper Clamp Voltage
I
SOURCE
= 0.5 mA
5.7
6.2
6.7
V
Lower Clamp Voltage
I
SINK
= 0.5 mA (2)
2.1
2.25
2.4
V
CURRENT SENSE COMPARATOR
I
CS
Input Bias Current
V
CS
= 0
-1
A
t
LEB
Leading Edge Blanking
100
200
300
ns
td
(H-L)
Delay to Output
120
ns
V
CSclamp
Current sense reference clamp
V
COMP
= Upper clamp,
V
VFF
= V
MULT
=0.5V
1.0
1.08
1.16
V
Vcs
offset
Current sense offset
V
MULT
= 0, V
VFF
= 3V
25
mV
V
MULT
= 3V, V
VFF
= 3V
5
V
CSdis
IC disable level
(2)
1.6
1.7
1.8
V
OUTPUT OVERVOLTAGE
I
OVP
Dynamic OVP triggering current
17
20
23
A
Hys
Hysteresis
(4)
15
A
Static OVP threshold
(2)
2.1
2.25
2.4
V
VOLTAGE FEEDFORWARD
V
VFF
Linear operation range
R
FF
=47 k
to GND
0.5
3
V
V
Dropout V
MULTpk
-V
VFF
10
mV
ZERO CURRENT DETECTOR
V
ZCDH
Upper Clamp Voltage
I
ZCD
= 2.5 mA
5.0
5.7
V
V
ZCDL
Lower Clamp Voltage
I
ZCD
= - 2.5 mA
-0.3
0
0.3
V
V
ZCDA
Arming Voltage
(positive-going edge)
(4)
1.4
V
V
ZCDT
Triggering Voltage
(negative-going edge)
(4)
0.7
V
I
ZCDb
Input Bias Current
V
ZCD
= 1 to 4.5 V
1
A
I
ZCDsrc
Source Current Capability
-2.5
mA
I
ZCDsnk
Sink Current Capability
2.5
mA
TRACKING BOOST FUNCTION
V
Dropout voltage V
VFF
-V
TBO
I
TBO
= 0.25 mA
10
mV
I
TBO
Linear operation
0
0.25
mA
Table 5. Electrical Characteristcs (continued)
(T
j
= -25 to 125C, V
cc
=12, C
o
= 1 nF between pin GD and GND, C
FF
=1F between pin V
FF
and GND;
unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
L6563
6/25
(1), (2) Parameters tracking each other
(3)
The multiplier output is given by:
(4)
Parameters guaranteed by design, functionality tested in production.
I
INV
-I
TBO
current mismatch
I
TBO
= 25 A to 0.25 mA
-3.5
3.5
%
V
TBOclamp
Clamp voltage
(2) V
VFF
= 4V
2.9
3
3.1
V
PFC_OK
V
thl
Latch-off threshold
(2) voltage rising
2.4
2.5
2.6
V
V
th
Disable threshold
(2) voltage falling
0.2
V
V
EN
Enable threshold
(2) voltage rising
0.26
V
I
PFC_OK
Input Bias Current
V
PFC_OK
= 0 to 2.5V
-0.1
-1
A
V
clamp
Clamp voltage
I
PFC_OK
= 1 mA
9
9.5
V
PWM_LATCH
I
leak
Low level leakage current
V
PWM_LATCH
=0
-1
A
V
H
High level
I
PWM_LATCH
= -0.5 mA
3.7
V
PWM_STOP
I
leak
High level leakage current
V
PWM_STOP
= 6V
1
A
V
L
Low level
I
PWM_STOP
= 0.5 mA
1
V
V
clamp
Clamp voltage
I
PFC_OK
= 2 mA
9
9.5
V
RUN FUNCTION
I
RUN
Input Bias Current
V
RUN
= 0 to 3 V
-1
A
V
DIS
Disable threshold
(2) voltage falling
0.5
0.52
0.54
V
V
EN
Enable threshold
(2) voltage rising
0.57
0.6
0.63
V
START TIMER
t
START
Start Timer period
75
150
300
s
GATE DRIVER
V
OHdrop
Dropout Voltage
I
GDsource
= 20 mA
2
2.6
V
I
GDsource
= 200 mA
2.5
3
V
V
OLdrop
I
GDsink
= 200 mA
1
2
V
t
f
Current Fall Time
30
70
ns
t
r
Current Rise Time
40
80
ns
V
Oclamp
Output clamp voltage
I
GDsource
= 5mA; Vcc = 20V
10
12
15
V
UVLO saturation
Vcc=0 to Vcc
On
, I
sink
=10mA
1.1
V
Table 5. Electrical Characteristcs (continued)
(T
j
= -25 to 125C, V
cc
=12, C
o
= 1 nF between pin GD and GND, C
FF
=1F between pin V
FF
and GND;
unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
C S
K
M
V
M U L T
V
C O M P
2.5
(
)
V
V F F
2
-----------------------------------------------------------
=
7/25
L6563
3
TYPICAL ELECTRICAL PERFORMANCE
Figure 5. Supply current vs. Supply voltage
Figure 6. IC consumption vs. Tj
Figure 7. Start-up & UVLO vs. Tj
Figure 8. Vcc Zener voltage vs. Tj
Figure 9. Feedback reference vs. Tj
Figure 10. E/A output clamp levels vs. Tj
Vcc(V)
0
0.005
0.01
0.05
0.1
0.5
1
5
10
Icc
(mA)
0
5
10
15
20
Co = 1nF
f = 70 kHz
T
j
= 25C
25
-50
0
50
100
150
0.02
0.05
0.1
0.2
0.5
1
2
5
10
Icc
(mA)
Operating
Quiescent
Disabled or
during OVP
Before start-up
Vcc = 12 V
Co = 1 nF
f = 70 kHz
Tj (C)
Latched off
Tj (C)
V
CC-ON
(V)
V
CC-OFF
(V)
-50
0
50
100
150
9
9.5
10
10.5
11
11.5
12
12.5
Tj (C)
Vcc
z
(pin 14)
(V)
-50
0
50
100
150
22
23
24
25
26
27
28
V
REF
(V)
-50
0
50
100
150
2.4
2.45
2.5
2.55
2.6
Vcc = 12 V
Tj (C)
(pin 1)
Tj (C)
V
COMP
(pin 2)
(V)
-50
0
50
100
150
1
2
3
4
5
6
7
Upper clamp
Lower clamp
Vcc = 12 V
L6563
8/25
Figure 11. Static OVP level vs. Tj
Figure 12. Dynamic OVP current vs. Tj
(normalized value)
Figure 13. Delay-to-output vs. Tj
Figure 14. Vcs clamp vs. Tj
Figure 15. Current-sense offset vs. mains
voltage phase angle
Figure 16. IC disable level on current
sense vs. Tj
Tj (C)
V
COMP
(pin 2)
(V)
-50
0
50
100
150
2
2.1
2.2
2.3
2.4
2.5
Vcc = 12 V
I
OVP
-50
0
50
100
150
80%
90%
100%
110%
120%
Vcc = 12 V
Tj (C)
Tj (C)
t
D(H-L)
(ns)
-50
0
50
100
150
50
100
150
200
250
300
Vcc = 12 V
Tj (C)
V
CSx (pin 4)
(V)
-50
0
50
100
150
1
1.1
1.2
1.3
1.4
1.5
Vcc = 12 V
V
COMP
= Upper clamp
(
)
V
CSoffset (pin 4)
(mV)
0
0.628
1.256
1.884
2.512
3.14
0
5
10
15
20
25
30
Vcc = 12 V
Tj = 25
V
MULT
= 0 to 3V
V
FF
= 3V
V
MULT
= 0 to 0.7V
V
FF
= 0.7V
Tj (C)
Vpin4
(V)
-50
0
50
100
150
1.0
1.2
1.4
1.6
1.8
2.0
Vcc = 12 V
9/25
L6563
Figure 17. Multiplier characteristics @ VFF=1V
Figure 18. Multiplier characteristics @ VFF=3V
Figure 19. Multiplier gain vs. Tj
Figure 20. ZCD clamp levels vs. Tj
Figure 21. ZCD source capability vs. Tj
Figure 22. VFF & TBO dropouts vs. Tj
V
MULT
(pin 3) (V)
V
COMP
(pin 2)
(V)
0
0.2
0.4
0.6
0.8
1
1.2
0
0.2
0.4
0.6
0.8
1
2.6
3.0
3.5
4.0
4.5
upper voltage
clamp
5.0
5.5
V
CS
(pin 4)
(V)
Vcc = 12 V
Tj = 25 C
V
MULT
(pin 3) (V)
V
COMP
(pin 2)
(V)
0
0.5
1
1.5
2
2.5
3
3.5
0
0.1
0.2
0.3
0.4
0.5
2.6
3.0
3.5
4.0
4.5
upper voltage
clamp
5.0
5.5
V
CS
(pin 4)
(V)
Vcc = 12 V
Tj = 25 C
K
M
Tj (C)
-50
0
50
100
150
0
0.2
0.4
0.6
0.8
1
Vcc = 12 V
V
COMP
=4 V
V
MULT
= V
FF
=1V
Tj (C)
V
ZCD (pin 11)
(V)
-50
0
50
100
150
-1
0
1
2
3
4
5
6
7
Vcc = 12 V
I
ZCD
= 2.5 mA
Upper clamp
Lower clamp
Tj (C)
I
ZCDsrc
(mA)
-50
0
50
100
150
-8
-6
-4
-2
0
Vcc = 12 V
V
ZCD
= lower clamp
Tj (C)
-50
0
50
100
150
-2
0
2
4
6
(mV)
Vpin5 - Vpin3
Vpin6 - Vpin5
Vcc = 12 V
Vpin3 = 2.9 V
L6563
10/25
Figure 23. TBO current mismatch vs. Tj
Figure 24. TBO-INV current mismatch vs.
TBO currents
Figure 25. TBO clamp vs. Tj
Figure 26. RUN thresholds vs. Tj
Figure 27. PWM_LATCH high saturation vs. Tj
Figure 28. PWM_STOP low saturation vs. Tj
Tj (C)
-50
0
50
100
150
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
I(INV)-I(TBO)
I(INV)
100
ITBO = 25 A
ITBO = 250 A
Vcc = 12 V
I(TBO)
0
100
200
300
400
500
600
-2.3
-2.2
-2.1
-2.0
-1.9
-1.8
-1.7
-1.6
Vcc = 12 V
Tj = 25 C
I(INV)-I(TBO)
I(INV)
100
Tj (C)
-50
0
50
100
150
2.5
2.75
3
3.25
3.5
Vcc = 12 V
Vpin3= 4 V
(V)
Vpin6
Tj (C)
-50
0
50
100
150
2.5
2.75
3
3.25
3.5
Vcc = 12 V
Vpin3= 4 V
(V)
Vpin6
Tj (C)
Vpin10
(V)
-50
0
50
100
150
0.0
0.2
0.4
0.6
0.8
1.0
Vcc = 12 V
ON
OFF
Tj (C)
Vpin10
(V)
-50
0
50
100
150
0.0
0.2
0.4
0.6
0.8
1.0
Vcc = 12 V
ON
OFF
Tj (C)
Vpin8
(V)
-50
0
50
100
150
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Vcc = 12 V
Isource = 50 A
Isource = 500 A
Tj (C)
Vpin8
(V)
-50
0
50
100
150
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Vcc = 12 V
Isource = 50 A
Isource = 500 A
Tj (C)
Vpin9
(V)
-50
0
50
100
150
0.0
1.0
2.0
3.0
4.0
5.0
Vcc = 12 V
Isink = 0.5 mA
0.50
0.40
0.30
0.20
0.10
0
Tj (C)
Vpin9
(V)
-50
0
50
100
150
0.0
1.0
2.0
3.0
4.0
5.0
Vcc = 12 V
Isink = 0.5 mA
0.50
0.40
0.30
0.20
0.10
0
11/25
L6563
Figure 29. PFC_OK thresholds vs. Tj
Figure 30. Start-up timer vs. Tj
Figure 31. Gate-drive clamp vs. Tj
Figure 32. UVLO saturation vs. Tj
Figure 33. Gate-drive output low saturation
Figure 34. Gate-drive output high saturation
Tj (C)
Vpin7
(V)
-50
0
50
100
150
0.1
0.2
0.3
0.5
1.0
2.0
3.0
Vcc = 12 V
ON
OFF
Latch-off
Tj (C)
Vpin7
(V)
-50
0
50
100
150
0.1
0.2
0.3
0.5
1.0
2.0
3.0
Vcc = 12 V
ON
OFF
Latch-off
Tj (C)
Tstart
(s)
-50
0
50
100
150
100
110
120
130
140
150
Vcc = 12 V
Tj (C)
Tstart
(s)
-50
0
50
100
150
100
110
120
130
140
150
Vcc = 12 V
Tj (C)
Vpin15
clamp
(V)
-50
0
50
100
150
10
10.5
11
11.5
12
Vcc = 20 V
Tj (C)
-50
0
50
100
150
0.5
0.6
0.7
0.8
0.9
1
1.1
Vcc = 0 V
Vpin15
(V)
V
pin15
(V)
0
200
400
600
800
1,000
0
1
2
3
4
I
GD
(mA)
Tj = 25 C
Vcc = 11 V
SINK
0
100
200
300
400
500
600
700
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
I
GD
(mA)
Tj = 25 C
Vcc = 11 V
SOURCE
Vcc - 2.0
Vcc - 2.5
Vcc - 3.0
Vcc - 3.5
Vcc - 4.0
V
pin15
(V)
L6563
12/25
4
APPLICATION INFORMATION
4.1 Overvoltage protection
Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal
value, set by the ratio of the resistors R1 and R2 of the output divider. Neglecting the ripple components,
under steady state conditions the current through R1 equals that through R2. Considering that the non-in-
verting input of the error amplifier is internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then:
.
If the output voltage experiences an abrupt change
Vo the voltage at pin INV is kept at 2.5V by the local
feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long
time constant. Then the current through R2 remains equal to 2.5/R2 but that through R1 becomes:
.
The difference current
I
R1
= I'
R1
- I'
R1
=
V
O
/R1 will flow through the compensation network and enter the
error amplifier (pin COMP). This current is monitored inside the IC and when it reaches about 18 A the out-
put voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the cur-
rent exceeds 20 A, the OVP is triggered (Dynamic OVP), and the external power transistor is switched off
until the current falls approximately below 5 A. However, if the overvoltage persists (e.g. in case the load
is completely disconnected), the error amplifier will eventually saturate low hence triggering an internal com-
parator (Static OVP) that will keep the external power switch turned off until the output voltage comes back
close to the regulated value. The output overvoltage that is able to trigger the OVP function is then:
V
O
= R1 20 10
-6
An important advantage of this technique is that the overvoltage level can be set independently of the reg-
ulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1.
Another advantage is the precision: the tolerance of the detection current is 15%, which means 15% tol-
erance on the
Vo. Since it is usually much smaller than Vo, the tolerance on the absolute value will be
proportionally reduced.
Example: Vo=400V,
Vo=40V. Then: R1=40V/20A=2M; R2=2.52M/(400-2.5)=12.58k. The toler-
ance on the OVP level due to the L6563 will be 400.15=6 V, that is 1.36%.
When either OVP is activated the quiescent consumption is reduced to minimize the discharge of the Vcc
capacitor.
Figure 35. Output voltage setting, OVP and FFP functions: internal block diagram
I
R2
I
R1
2.5
R 2
--------
V
O
2.5
R1
----------------------
=
=
=
I'
R1
V
O
2.5
V
O
+
R 1
----------------------------------------
=
-
+
2.5V
L6563
1
2
INV
COMP
E/A
+
-
Frequency
Compensation
+
-
R2
7
PFC_OK
I
TBO
-
+
2.25V
Static OVP
-
+
Dynamic OVP
20 A
Vout
{
R1a
R1b
R1
9.5V
FAULT (latched)
TBO
FUNCTION
R4
{
R3a
R3b
R3
+
-
FAULT (not latched)
0.26V
9.5V
13/25
L6563
4.2 Feedback failure protection (FFP)
The OVP function above described is able to handle "normal" overvoltage conditions, i.e. those resulting
from an abrupt load/line change or occurring at start-up. It cannot handle the overvoltage generated, for
instance, when the upper resistor of the output divider (R1) fails open: the voltage loop can no longer read
the information on the output voltage and will force the PFC pre-regulator to work at maximum ON-time,
causing the output voltage to rise with no control.
A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the output voltage
with a separate resistor divider (R3 high, R4 low, see
Figure 35
). This divider is selected so that the voltage
at the pin reaches 2.5V if the output voltage exceeds a preset value, usually larger than the maximum Vo
that can be expected, also including worst-case load/line transients.
Example: Vo = 400 V, Vox = 475 V. Select: R3=3M
; then: R4=3M 2.5/(475-2.5)=15.87k.
When this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its
quiescent consumption is reduced below 250 A and the condition is latched as long as the supply voltage
of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high.
PWM_LATCH is an open source output able to deliver 3.7V min. with 0.5 mA load, intended for tripping a
latched shutdown function of the PWM controller IC in the cascaded DC-DC converter, so that the entire
unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltages
of both the L6563 and the PWM controller go below their respective UVLO thresholds.
The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will shut down the
IC, reducing its consumption below 1 mA. In this case both PWM_STOP and PWM_LATCH keep their
high impedance status. To restart the IC simply let the voltage at the pin go above 0.26 V.
Note that this function offers a complete protection against not only feedback loop failures or erroneous
settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short
or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator.
4.3 Voltage Feedforward
The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the
crossover frequency f
c
of the overall open-loop gain because the gain has a single pole characteristic. This
leads to large trade-offs in the design.
For example, setting the gain of the error amplifier to get f
c
= 20 Hz @ 264 Vac means having f
c
4 Hz @
88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient
current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This
limit is considered when selecting the sense resistor to let the full load power pass under minimum line
voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line,
whereas a fixed power limit requires the current limit to vary inversely with the line voltage.
Voltage Feedforward can compensate for the gain variation with the line voltage and allow overcoming all
of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage,
feeding this voltage into a squarer/divider circuit (1/V
2
corrector) and providing the resulting signal to the
multiplier that generates the current reference for the inner current control loop (see
Figure 36
).
Figure 36. Voltage feedforward: squarer-divider (1/V
2
) block diagram and transfer characteristic
0
1
2
3
4
0
0.5
1
1.5
2
V
FF
=V
MULT
Vcsx
0.5
V
COMP
=4V
Actual
Ideal
5
MULT
3
R5
Rectified mains
R6
"ideal" diode
current
reference
(Vcsx)
9.5V
VFF
C
FF
R
FF
E/A output
(V
COMP
)
-
+
1/V
2
MULTIPLIER
L6563
L6563
14/25
In this way a change of the line voltage will cause an inversely proportional change of the half sine ampli-
tude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be
halved and vice versa) so that the current reference is adapted to the new operating conditions with (ide-
ally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be con-
stant throughout the input voltage range, which improves significantly dynamic behavior at low line and
simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has
its own time constant. If it is too small the voltage generated will be affected by a considerable amount of
ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD
and poor PF); if it is too large there will be a considerable delay in setting the right amount of feedforward,
resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large
line voltage changes. Clearly a trade-off is required.
The L6563 realizes Voltage Feedforward with a technique that makes use of just two external parts and
that limits the feedforward time constant trade-off issue to only one direction. A capacitor C
FF
and a resis-
tor R
FF
, both connected from the VFF (#5) pin to ground, complete an internal peak-holding circuit that
provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (#3). R
FF
provides
a means to discharge C
FF
when the line voltage decreases (see
Figure 36
). In this way, in case of sudden
line voltage rise, C
FF
will be rapidly charged through the low impedance of the internal diode and no ap-
preciable overshoot will be visible at the pre-regulator's output; in case of line voltage drop C
FF
will be dis-
charged with the time constant R
FF
C
FF
, which can be in the hundred ms to achieve an acceptably low
steady-state ripple and have low current distortion; consequently the output voltage can experience a con-
siderable undershoot, like in systems with no feedforward compensation.
The twice-mains-frequency (2f
L
) ripple appearing across C
FF
is triangular with a peak-to-peak amplitude
that, with good approximation, is given by:
,
where f
L
is the line frequency. The amount of 3
rd
harmonic distortion introduced by this ripple, related to
the amplitude of its 2f
L
component, will be:
Figure 37
shows a diagram that helps choose the time constant R
FF
C
FF
based on the amount of maxi-
mum desired 3
rd
harmonic distortion. Always connect R
FF
and C
FF
to the pin, the IC will not work properly
if the pin is either left floating or connected directly to ground.
Figure 37. R
FF
C
FF
as a function of 3
rd
harmonic distortion introduced in the input current
The dynamics of the voltage feedforward input is limited downwards at 0.5V (see
Figure 36
), that is the
output of the multiplier will not increase any more if the voltage on the V
FF
pin is below 0.5V. This helps to
prevent excessive power flow when the line voltage is lower than the minimum specified value
V
FF
2V
MULTpk
1
4f
L
R
FF
C
FF
+
----------------------------------------
=
D
3
%
100
2
f
L
R
FF
C
FF
----------------------------------
=
D %
3
0.1
1
10
0.01
0.1
1
10
f = 50 Hz
L
f = 60 Hz
L
R C [s]
FF
FF
15/25
L6563
4.4 THD optimizer circuit
The L6563 is provided with a special circuit that reduces the conduction dead-angle occurring to the AC
input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total
Harmonic Distortion) of the current is considerably reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively when the instan-
taneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after
the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be
reverse-biased and the input current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy near the line volt-
age zero-crossings as compared to that commanded by the control loop. This will result in both minimizing
the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor
after the bridge.
Figure 38. THD optimization: standard TM PFC controller (left side) and L6563 (right side)
Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to
the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the
instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the
top of the sinusoid. Furthermore the offset is modulated by the voltage on the V
FF
pin (see
Voltage Feed-
forward
section) so as to have little offset at low line, where energy transfer at zero crossings is typically
quite good, and a larger offset at high line where the energy transfer gets worse.
The effect of the circuit is shown in
Figure 38
, where the key waveforms of a standard TM PFC controller
are compared to those of this chip.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge
rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces
a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC
pre-regulator - thus reducing the effectiveness of the optimizer circuit.
Imains
Vdrain
Imains
Vdrain
Input current
Input current
MOSFET's drain voltage
MOSFET's drain voltage
Rectified mains voltage
Rectified mains voltage
Input current
Input current
L6563
16/25
4.5 Tracking boost function
In some applications it may be advantageous to regulate the output voltage of the PFC pre-regulator so
that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators.
This is commonly referred to as "tracking boost" or "follower boost" approach.
With the L6563 this can be realized by connecting a resistor (R
T
) between the TBO pin and ground. The
TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the
mains RMS voltage. The resistor defines a current, equal to V(TBO)/R
T
, that is internally 1:1 mirrored and
sunk from pin INV (#1) input of the L6563's error amplifier. In this way, when the mains voltage increases
the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connect-
ed between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the
PFC pre-regulator will be forced to get higher. Obviously, the output voltage will move in the opposite di-
rection if the input voltage decreases.
To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the
voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the
maximum input voltage above which input-to-output tracking ends and the output voltage becomes con-
stant. If this function is not used, leave the pin open: the device will regulate a fixed output voltage.
Starting from the following data:
Vin
1
= minimum specified input RMS voltage;
Vin
2
= maximum specified input RMS voltage;
Vo
1
= regulated output voltage @ Vin = Vin1;
Vo
2
= regulated output voltage @ Vin = Vin2;
Vox = absolute maximum limit for the regulated output voltage;
Vo = OVP threshold,
to set the output voltage at the desired values use the following design procedure:
1) Determine the input RMS voltage Vin
clamp
that produces Vo = Vox:
and choose a value Vin
x
such that Vin
2
= Vin
x
< Vin
clamp
. This will result in a limitation of the output volt-
age range below Vox (it will equal Vox if one chooses Vin
x
= Vin
clamp
)
2) Determine the divider ratio of the MULT pin (#3) bias:
and check that at minimum mains voltage Vin
1
the peak voltage on pin 3 is greater than 0.65V.
3) Determine R1, the upper resistor of the output divider:
.
4) Calculate the lower resistor R2 of the output divider and the adjustment resistor R
T
:
.
5) Check that the maximum current sourced by the TBO pin (#6) does not exceed the maximum specified (0.25 mA):
.
In the following Mathcad sheet, as an example, the calculation is shown for the circuit illustrated in
Figure
39.
Figure 40
shows the internal block diagram of the tracking boost function.
Vin
clamp
Vox
Vo
1
Vo
2
Vo
1
---------------------------- Vin
2
Vo x
Vo
2
Vo
2
Vo
1
---------------------------- Vin
1
=
k
3
2 Vin
x
------------------------
=
R1
Vo
20
----------- 10
6
=
R2
2.5 R1
Vin
2
Vin
1
Vo
1
2.5
(
) Vin
2
Vo
2
2.5
(
) Vin
1
---------------------------------------------------------------------------------------------------
=
R
T
2 k R 1
Vin
2
Vin
1
Vo
2
Vo
1
-------------------------------
=
I
TBOmax
3
R
T
-------
0.25 10
3
=
17/25
L6563
Design Data
Vin
1
:=88V
Vo
1
:= 200V
Vin
2
:=264V
Vo
2
:= 385V
Vox;=400V
Vo;=40V
Step 1
Vin
clamp
= 278.27V
choose:
Vin
x
: = 270V
Step 2
k = 7.857 x 10
-3
Step 3
R1 = 2 x 10
6
Step 4
R2 = 4.762 x 10
4
R
T
= 2.114 x 10
4
Step 5
I
TBOmax
= 0.142 mA
Vo(Vi): =
Vo(Vin
1
) = 200 V
Vo(Vin
2
) = 385 V
Vo(Vin
X
) = 391.307 V
Vin
clamp
:
Vox
Vo
1
Vo
2
Vo
1
---------------------------- Vin
2
=
Vo x
Vo
2
Vo
2
Vo
1
---------------------------- Vin
1
k:
3
2 Vin
x
------------------------
=
R1:
Vo
20
----------- 10
6
=
R2:
2.5 R1
Vin
2
Vin
1
Vo
1
2.5
(
) Vin
2
Vo
2
2.5
(
) Vin
1
---------------------------------------------------------------------------------------------------
=
R
T
:
k
2 R1
Vin
2
Vin
1
Vo
2
Vo
1
-------------------------------
=
I
TBOmax
:
3
R
T
------- 10
3
=
V
MULTpk
k
2 Vi
V
TBO
if V
MULTpk
3,V
MULTpk
,3
<
(
)
2.5
1
R1
R2
--------
+
V
TBO
R 1
R
T
--------
+
100
150
200
250
300
200
250
300
350
400
Vo 2
Vo Vin
(
)
Vin 2
Vin x
Vin
Vox
L6563
18/25
Figure 39. 80W, wide-range-mains PFC pre-regulator with tracking boost function active
Figure 40. Tracking boost and Voltage Feedforward blocks
4.6 Inductor saturation detection
Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope be-
comes so large (50-100 times steeper, see
Figure 41
) that during the current sense propagation delay the
current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense
resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dis-
sipate a huge amount of power, which leads to a catastrophic failure after few switching cycles.
A well-designed boost inductor must not saturate even under the worst-case operating conditions, that is
at power-up with maximum load and minimum line voltage, when the error amplifier saturates high and
commands the maximum peak current (defined by the current reference clamp, V
CSclamp
, and the sense
resistor) for some line cycles. However, especially in the development stage, inductor saturation may be
encountered and a protection able to prevent the application from blowing up can be very useful.
The device is provided with a second comparator on the current sense pin (CS, #4) that stops and latches
off the IC if the voltage on the pin, normally limited within 1.1V, exceeds 1.7V. Also the cascaded DC-DC
converter can be stopped via the PWM_LATCH pin that is asserted high. In this way there can be abnor-
mal current only for one cycle, after that the system is stopped and enabled to restart only after recycling
the input power, that is when the Vcc voltages of the IC and the PWM controller go below their respective
UVLO thresholds. System safety will be considerably increased.
14
3
BRIDGE
4 x 1N4007
C1
0.22 F
400V
C3
22
F
25V
FUSE
4A/250V
R3
68 k
T
11
12
L6563
13
2
1
C6 100 nF
R6
10
MOS
STP8NM50
4
C6
56 F
400V
Vo=200 to 385 V
Po=80W
Vac
(88V to 264V)
R7a,b
0.68
1/4 W
R9
47.5 k
+
-
C2
2.2nF
D1
STTH1L06
NTC
R5
62 k
C5
1 F
5
C4
470 nF
6
7
10
8
9
R4
21 k
R8b
1 M
Supply Voltage
10.3 to 22V
R8a
1 M
C7
10 nF
R10b
3.3 M
R10a
3.3 M
R11
34.8 k
R1b
3.3 M
R1a
3.3 M
R2
51.1 k
R10
390 k
R1
L6563
INV
1
Vout
TBO
6
1:1 CURRENT
MIRROR
R
T
2.5V
E/A
+
-
COMP
2
3V
-
+
5
I
TBO
I
R1
MULT
3
R5
Rectified mains
R6
"ideal"
diode
MULTIPLIER
1/V
2
current
reference
R2
I
R2
I
TBO
9.5V
9.5V
VFF
C
FF
R
FF
19/25
L6563
Figure 41. Effect of boost inductor saturation on the MOSFET current and detection method
4.7 Power management/housekeeping functions
A special feature of this IC is that it facilitates the implementation of the "housekeeping" circuitry needed
to coordinate the operation of the PFC stage to that of the cascaded DC-DC converter. The functions re-
alized by the housekeeping circuitry ensure that transient conditions like power-up or power down se-
quencing or failures of either power stage be properly handled.
This device provides some pins to do that. As already mentioned, one communication line between the IC
and the PWM controller of the cascaded DC-DC converter is the PWM_LATCH pin, which is normally
open when the PFC works properly and goes high if it loses control of the output voltage (because of a
failure of the control loop) or if the boost inductor saturates, with the aim of latching off the PWM controller
of the cascaded DC-DC converter as well (
Feedback failure protection (FFP)
for more details ).
A second communication line can be established via the disable function included in the PFC_OK pin
(
Feedback failure protection (FFP)
for more details ). Typically this line is used to allow the PWM con-
troller of the cascaded DC-DC converter to shut down the L6563 in case of light load, to minimize the no-
load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut
down the supply voltage. Interface circuits like those shown in
Figure 42
, where the L6563 works along
with the L5991, PWM controller with standby function, can be used. Needless to say, this operation as-
sumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or,
in other words, that the DC-DC stage starts first, it powers both controllers and enables/disables the op-
eration of the PFC stage.
Figure 42. Interface circuits that let the L5991/ L5991A disable the L6563 at light load (slave PFC)
The third communication line is the PWM_STOP pin (#9), which works in conjunction with the RUN pin
(#10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the
cascaded DC-DC converter. The pin is an open collector, normally open, that goes low if the device is
disabled by a voltage lower than 0.52V on the RUN pin. It is important to point out that this function works
correctly in systems where the PFC stage is the master and the cascaded DC-DC converter is the slave
or, in other words, where the PFC stage starts first, powers both controllers and enables/disables the op-
T
delay
I
L
Multiplier
Output
Vcs
t
1.7V
T
delay
Multiplier
Output
Vcs
t
I
L
1.7V
T
delay
Multiplier
Output
Vcs
t
I
L
1.7V
Inductor not saturating
Inductor slightly saturating
Inductor saturating hard
L5991/A
ST-BY
4
16
27
k
Vref
L6563
PFC_OK
7
100 k
150 k
150 k
47
k
100 nF
BC547
BC547
BC557
L5991/A
ST-BY
4
16
27
k
Vref
L6563
Vcc
14
100 k
150 k
150 k
15
k
100 nF
BC557
BC547
BC557
100 nF
Supply_Bus
L6563
20/25
eration of the DC-DC stage.
This function is quite flexible and can be used in different ways. In systems comprising an auxiliary con-
verter and a main converter (e.g. desktop PC's silver box or hi-end LCD-TV), where the auxiliary converter
also powers the controllers of the main converter, the pin RUN can be used to start and stop the main
converter. In the simplest case, to enable/disable the PWM controller the PWM_STOP pin can be con-
nected to either the output of the error amplifier (
Figure 43 a
) or, if the chip is provided with it, to its soft-
start pin (
Figure 43
b
). The use of the soft-start pin allows the designer to delay the start-up of the DC-DC
stage with respect to that of the PFC stage, which is often desired. An underlying assumption in order for
that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of
the L6563.
Figure 43. Interface circuits that let the L6563 switch on or off a PWM controller (master PFC)
If this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents
the DC-DC stage from starting up correctly) or, simply, the PWM controller is devoid of soft start, the ar-
rangement of
Figure 44
lets the DC-DC converter start-up when the voltage generated by the PFC stage
reaches a preset value. The technique relies on the UVLO thresholds of the PWM controller.
Figure 44. Interface circuits for actual power-up sequencing (master PFC)
Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC stage is the
master) is brownout protection, thanks to the hysteresis provided.
Brownout protection is basically a not-latched device shutdown function that must be activated when a
condition of mains undervoltage is detected. This condition may cause overheating of the primary power
section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open
loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input
voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during
converter power down and that cause the output voltage of the converter not to decay to zero monotoni-
cally. For these reasons it is usually preferable to shutdown the unit in case of brownout.
a)
b)
L6563
10
9
OFF
ON
PWM
controller
X
L5991/A: X=6
UC284x: X=1
UC384x: X=1
L6565:
X=2
RUN
PWM_STOP
C
SS
L6563
OFF
ON
L5991/A
7 SS
10
9
RUN
PWM_STOP
Supply rail
10 k
BC558C
BC337
VZ1
L6563
10
OFF
ON
14
9
7
PWM
controller
L5991/A:
X=8+9
UC284x: X=7
UC384x: X=7
L6565:
X=8
L6598: X=12
X
RUN
Vcc
PWM_STOP
PF
C
_
O
K
HV bus
VZ2
VZ1 < UVLO, VZ2 < 9 V
VZ1 + VZ2 < Vccmax
21/25
L6563
IC shutdown upon brownout can be easily realized as shown in
Figure 45.
The scheme on the left is of
general use, the one on the right can be used if the bias levels of the multiplier and the R
FF
C
FF
time con-
stant are compatible with the specified brownout level and with the specified holdup time respectively.
In
Table 6
it is possible to find a summary of all of the above mentioned working conditions that cause the
device to stop operating.
Figure 45. Brownout protection (master PFC)
Table 6. Summary of L6563 idle states
5
APPLICATION EXAMPLES AND IDEAS
Figure 46. 250W, wide-range-mains PFC pre-regulator with fixed output voltage
CONDITION
CAUSED OR
REVEALED BY
PWM_LATCH
(pin 8)
PWM_STOP
(pin9)
TYPICAL IC
CONSUMPTION
IC behavior
UVLO
Vcc < 8.7 V
Open
Open
50 A
Auto-restart
Feedback
disconnected
PFC_OK > 2.5 V
Active (high)
Open
180 A
Latched
Saturated Boost
Inductor
Vcs > 1.7 V
Active (high)
Open
180 A
Latched
AC Brownout
RUN < 0.52 V
Open
Active (low)
1.5 mA
Auto-restart
Standby
PFC_OK < 0.2 V
Open
Open
1.5 mA
Auto-restart
10
RUN
AC mains
L6563
VFF
L6563
5
RUN
10
R
FF
C
FF
14
3
B1
KBU8M
R1A
820 k
C1
1 F
400V
C2
1 F
FUSE
8A/250V
R3
47 k
11
12
L6563
13
2
1
M1
STP12NM50
4
R9A
1 M
C8
150 F
450 V
Vout = 400V
Pout = 250 W
Vac
88V
to
264V
R8A,B
0.22
1 W
R10
12.7 k
+
-
C3
10nF
D2
STTH5L06
R6 33
C4
1 F
R1B
820 k
R2
10 k
D3 1N4148
R9B
1 M
NTC1
2.5
D1
1N5406
C6
470 nF
630 V
R5
6.8 k
L1
R4
1 M
Vcc
10.3 to 22 V
R11A
1.87 M
R12
20 k
R11B
1.87 M
6
7
5
R7
390 k
C5
470nF
8
9
C7
10 nF
10
Boost Inductor (L1) Spec
ETD29x16x10 core, 3C85 ferrite or equivalent
1.5 mm gap for 150 H primary inductance
Primary: 74 turns 20xAWG30 (
0.3 mm)
Secondary: 8 turns 0.1 mm
L6563
22/25
Figure 47. 350W, wide-range-mains PFC pre-regulator with fixed output voltage and FOT control
14
3
B1
KBU8M
R1A
620 k
C1
1 F
400V
C2
1 F
FUSE
8A/250V
R8
1.5 k
11
12
L6563
13
2
1
M1A
STP12NM50
4
C11
220 F
450 V
Vout = 400V
Pout = 350W
Vac
88V
to
264V
R12A,B,C
0.33
1 W
+
-
C3
10nF
D2
STT H806DTI
R9 6.8
C5
1 F
R1B
620 k
R2
10 k
D3 1N4148
D5
1N4148
R7
12 k
C7
560 pF
C6 330 pF
NTC1
2.5
D1
1N5406
C9
470 nF
630 V
R5
6.8 k
R10 6.8
D4
1N4148
M1B
STP12NM50
R6
1.5 k
TR1
BC557
L1
R15A
1.87 M
R16
20 k
R15B
1.87 M
6
7
5
R3
390 k
C4
470nF
9
8
9
C10
10 nF
10
C8
330 pF
R11 330
R13A
1 M
R14
12.7 k
R13B
1 M
R4
1 M
Vcc
10.3 to 22 V
L1: core E42*21*15, B2 material
1.9 mm air gap on centre leg, main winding
inductance 0.55 mH
58 T of 20 x AWG32 (
0.2 mm)
23/25
L6563
6
PACKAGE INFORMATION
Figure 48. SO14 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.35
1.75
0.053
0.069
A1
0.10
0.30
0.004
0.012
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.01
D
(1)
8.55
8.75
0.337
0.344
E
3.80
4.0
0.150
0.157
e
1.27
0.050
H
5.8
6.20
0.228
0.244
h
0.25
0.50
0.01
0.02
L
0.40
1.27
0.016
0.050
k
0 (min.), 8 (max.)
ddd
0.10
0.004
(1) "D" dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO14
0016019 D
L6563
24/25
7
REVISION HISTORY
Table 7. Revision History
Date
Revision
Description of Changes
November 2004
1
First Issue
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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25/25
L6563
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