L6353
SMART DRIVER FOR POWER MOS & IGBT
PEAK HIGH OUTPUT CURRENT CAPABIL-
ITY (+8A)
WIDE SUPPLY VOLTAGE RANGE (12.5 TO
18V)
0 TO 7.5V NEGATIVE BIAS VOLTAGE SUP-
PLY RANGE
OVER
CURRENT
AND
DESATURATION
PROTECTION OF THE EXTERNAL POWER
DEVICE (EXTERNALLY PROGRAMMABLE)
LATCH-UP PROTECTION (FOR IGBT)
TWO STEPS TURN-ON (PROGRAMMABLE)
PROTECTION AGAINST POSITIVE SUPPLY
UNDER-VOLTAGE
INPUT COMPATIBLE WITH OPTOCOUPLER
OR PULSE TRANSFORMER
PROGRAMMABLE TURN-ON DELAY
THERMAL PROTECTION WITH ON-CHIP
OVER-TEMPERATURE ALARM AND TURN-
OFF PROCEDURE
OPERATING FREQUENCY UP TO 100kHz
DESCRIPTION
The L6353 device is a smart driver, with all the
drive and protection know-how "on board".
Available in both DIP and SO package, it can be
triggered with a logic level or with the signal from an
optocoupler or a pulse transformer. It filters parasitic
input signals and drives any MOS or IGBT.
February 2000
DIP16
2.5V
300
A
+
-
1.25V
FILTER
200ns
1.25V
3.75V
3.15V
+
-
LOGIC
+
-
+
-
4V
ON_SENSE
ON_LEV_PROG
MON_DELAY
V
SS
OUT2
OUT1
V
POS
ALARM
INV_OUT
INPUT
SELECT
DELAY
COM
D94IN106B
OUT1
CLAMPING
CLAMP_PROG
THERMAL
SHUTDOWN
+
-
3.15V
7.5V
-
+
SUPPLY
UV SENSE
REFERENCES
REF
V
CC
BLOCK DIAGRAM
SO16
ORDERING NUMBERS: L6353 (DIP)
L6353D (SO)
1/11
DESCRIPTION (continued)
It monitors the on-state voltage drop of the driven
power device and protects it against overload and
short circuit.
The on-state voltage drop level is externally pro-
grammable from 5 to 15V. This function is inhib-
ited during the turn-on of the external power de-
vice for an externally programmable period.
An internal inhibition time of 200ns avoids false
triggering.
Overload or overheating are signalled on an
alarm output. If temperature continues to increase
the power output is switched off and maintained
in the off-state until the temperature decreases
below the low threshold. A programmable turn-on
delay avoids cross conduction in bridge configu-
rations.
To preserve the external power device (especially
IGBT) from the risk of latch-up, the gate voltage
can be risen in two different steps (of which the
first is externally programmable from 7 to 11V).
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage referred to COM pin
20
V
V
SS
Negative Supply Voltage referred to COM pin
8 to 0
V
V
POS
- V
OUT1
Collector-Emitter Voltage of High Side NPN
25
V
V
OUT2
- V
SS
Drain-Source Voltage of Low Side DMOS
25
V
V
EXT1
Externally Forced Voltage (pin 9)
-0.3 to V
CC
V
V
EXT2
Externally Forced Voltage (pins 4,7,10, 11, 12)
-0.3 to 7
V
I
DELAY
Sink Current pin Delay
3
mA
I
MON_DELAY
Sink Current Pin Mon_Delay
3
mA
V
ON_SENSE
Voltage on ON_SENSE Pin
VSS-0.3 to V
CC
V
I
OUT1
Positive Output Current (tp
1ms) (peak)
8
A
I
OUT2
Negative Output Current (tp
1ms) (peak)
8
A
I
INV_OUT
Output Current in INV_OUT Pin
20
mA
I
ALARM
Output Current in ALARM Pin
20
mA
P
tot
Total Power Dissipation
internally limited
T
amb
Operating Temperature Range
-25 to +85
C
T
stg
Storage Temperature
-50 to +150
C
THERMAL DATA
Symbol
Parameter
DIP16
SO16
Unit
R
thj-ambient
Thermal Resistance Junction-ambient
Max
80
90
C/W
OUT1
V
CC
V
POS
MON_DELAY
ALARM
VREF
INV_OUT
1
3
2
4
5
6
7
SELECT
V
SS
ON_SENSE
COM
OUT2
CLAMP_PROG
ON_LEV_PROG
16
15
14
13
12
10
11
D94IN113A
DELAY
8
INPUT
9
PIN CONNECTION (top view)
L6353
2/11
PIN FUNCTIONS
N.
Name
Function
1
OUT1
Output of high side driver (emitter of power NPN transistor).
2
V
CC
Positive Supply Voltage (referred to COM).
See under voltage lockout functioning
3
V
POS
Positive Bias Voltage (collector of the NPN power transistor).
4
CLAMP_PROG
First Step of the Gate Voltage Programming.
The programming is achieved setting an appropriate voltage on this pin (i.e. using a resistence
voltage divider).
5
INV-OUT
Inverted Output Driver Status.
The buffer output is able to drive some auxiliary circuit (i.e. a LED).
6
ALARM
Diagnostic Output Signal. A fault condition is signalled by this output buffer.
7
MON_DELAY
V
ON
Monitor Delay. An R-C network connected between this, the COM and the V
REF
pins,
define t
MON_DELAY
time interval (see fig 4)
8
V
REF
Output of the 5V/10mA internal voltage reference.
9
INPUT
Input signal.
The driving signal can be a logic level either active LOW (inverted mode) or HIGH (direct
mode) in the Logic Level or a pulse in the Pulse Transformer Mode (see Figure 2)
10
DELAY
On Triggering Delay. An R-C network connected between this, the COM and the V
REF
pins,
definethe t
DELAY
time interval (see fig 4)
11
SELECT
Select the direct/inverted mode in the Logic Level Mode. It's also the reference pin in Pulse
transformer mode.
12
ON_LEV_PROG
V
ON
level programming.
This pin is used to set the V
ON
monitor level. The programming is achieved setting an
appropriate voltage on this pin (i.e. using a resistive divider).
13
ON_SENSE
On State Monitor.
This pin is used to monitor the turning on of the external power device.
14
V
SS
Negative supply voltage (referred to the COM).
This pin is the source of the low side driver DMOS.
15
COM
Ground
16
OUT2
Output of the low side driver (drain of the DMOS).
L6353
3/11
DC ELECTRICAL CHARACTERISTICS (V
POS
= V
CC
=15V; V
SS
= -5 to 0V; T
j
= -25 to +125
C; unless
otherwise specified)
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
drop
1
V
POS
- V
OUT1
I
OUT1
= 2A
2.5
V
V
CC
2
Operating Supply Voltage
(referred to COM pin)
12.5
18
V
V
CCth1
Under Voltage Upper
Threshold
10.5
11.5
12.5
V
V
CCth2
Under Voltage Lower
Threshold
10
11
12
V
V
CChys
Under Voltage Hysteresis
0.3
0.5
0.7
V
I
CCq
Quiescent Supply Current
5
mA
V
d
4, 12
Output Voltage
pin floating
1.26
V
I
so
Sourced Current
pin grounding
20
A
I
si
Sinked Current
pin at +5V
-20
A
V
drop_sig
5, 6
High State Output Voltage Drop
I
out
= 20mA
V
CC
3
V
Low State Output Voltage Drop
3
V
V
ref
8
Output of Internal Voltage
Reference
I
ref
= 0A; T
j
= 25
C
4.9
5
5.1
V
I
ref
< 10mA; T
j
= 25
C
4.8
5.2
mA
R
in
7, 10
Comparator Input Resistance
100
V
dth
Comparator Threshold
3.15
V
R
ins
13
Input Resistance
75
K
I
outs
Output Current
pin grounded
200
A
V
SS
14
Operating Negative Bias
Voltage
(referred to COM)
7
0
V
R
ON
16
On Resistance
OUT2 to V
SS
); I
OUT2
= 2A
0.5
V
il
9
Low Level Voltage
(Logic Level Mode)
0
1
V
V
ih
High Level Voltage
(Logic Level Mode)
4
V
CC
V
I
in
Input Current
0<V
in
<V
CC
(Logic Level Mode)
10
10
A
t
inh
Inhibited Parasitic Pulse
Duration
(Logic Level Mode)
200
300
ns
V
ton
Turn-on Threshold Voltage
Referred to V
se l
(Pulse Transformer Mode)
1.5
V
V
toff
Turn-off Threshold Voltage
Referred to Vsel
(Pulse Transformer Mode)
1.5
V
V
sl
11
Low Level Voltage
(Logic Level Mode)
0
1
V
V
sh
High Level Voltage
(Logic Level Mode)
2
V
REF
V
I
sl
Current Output of SELECT Pin
V
sl
= 0V (Logic Level Mode)
300
A
V
sel
Output Voltage of SELECT Pin
(Pulse Transformer Mode)
2.25
2.5
2.75
V
L6353
4/11
AC ELECTRICAL CHARACTERISTICS
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
t
on
9 vs 1
Turn on Propagation Delay
Time
400
ns
t
off
9 vs 16
Turn off propagation delay
time
400
ns
t
r
1,16
Rise Time
50
ns
t
f
Fall Time
50
ns
t
fault
Delay Time for Fault
Detection
400
ns
THERMAL PROTECTION
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
T
th1
Over Temperature Threshold
(Thermal Procedure)
130
C
T
hys1
Over Temperature Threshold Hysteresis
20
C
T
th2
Over Temperature Shutdown
160
C
T
hys2
Over Temperature Shutdown Hysteresis
20
C
50%
50%
t
OFF
t
ON
t
90%
90%
10%
10%
tf
tr
t
V
in
V
OUT
D94IN107
50%
50%
t
W
0
5V
Figure 1: Switching waveforms and test circuit
INPUT
V
CC
V
POS
POSITIVE
SUPPLY
100
F
V
REF
V
in
1nF
D94IN108B
OUT1
OUT2
VCLAMP_
PROG
MON_
DELAY
V
SS
100
F
NEGATIVE
SUPPLY
SELECT
100nF
V
REF
100nF
DELAY
4.7K
4.7K
V
REF
COM
VON_SENSE
13
1
16
15
10
7
4
14
9
8
11
2
3
D.U.T.
Figure 1a : Switching waveforms and test circuit
L6353
5/11
V
in
INPUT
SELECT
V
in
V
ton
= V
sel
+1.5V
V
sel
OFF
t
W
t
W
V
toff
= V
sel
-1.5V
ON
D94IN114
INPUT PULSE
TRANSFORMER
t
Figure 2. Pulse Transformer mode operation.
V
OUT1
V
POS
V
CL
t
t
DELAY
D94IN115
V
in
V
SS
V
G
V
POS
V
CL
t
t
r
V
MILLER
V
SS
V
CE
/V
DS
V
H.V.
V
ONth
t
t
rr
t
MILLER
t
MON_DELAY
t
Short circuit
or overcurrent
protected area
Figure 3. Gate driving voltage waveforms.
t
MILLER
=
Q
GATE
R
G
'
V
CL
-
V
MILLER
Q
GATE
(device dependent)
defined between 0V and
V
CL
L6353
6/11
INPUT INTERFACE
To drive the external power device three different
possibilities are allowed:
The Logic Level Mode, either direct or inverted,
and the Pulse Transformer Mode
Using the Logic Level Mode (direct) an high level
(referred to COM), at the INPUT pin will start the
Turn on Procedure (i.e. firing an N channel exter-
nal device). A low level (referred to COM) will in-
stead close the OUT2 pin to VSS.
The functioning is reversed in the inverted mode.
To select the direct mode the SELECT pin must
be connected via a capacitor to COM. The in-
verted mode is chosen by connecting the SE-
LECT pin to COM.
In logic Level Mode pulses lasting less than t
inh
(200ns typ.) are filtered out.
In the Pulse Transformer Mode the SELECT pin
will be the reference pin for the signal applied to
the INPUTpin. The positive pulse will start the
TURN ON PROCEDURE, while the negative
pulse will close OUT2 to V
SS
. The duration of this
pulses (t
w
, see fig.2) must be again t
w
> t
inh
.
TURN-ON PROCEDURE
The firing of the external power device is per-
formed in three steps in order to avoid the most
common problems that can arise.
In each of these steps there are a number of pa-
rameters that can be easily externally presetted to
the requested values.
First Step
Parameter: t
DELAY
In order to avoid cross-conduction between the
external power device in half bridge arrangement
the driver output is activated after an externally
programmable delay time (t
DELAY
, see fig. 3) after
the input signal. To set the t
DELAY
interval an R-C
network has to be connected between the DE-
LAY, V
REF
and COM pins (see fig.4) giving:
t
DELAY
(
sec) = R
EXT
(K
) . C
EXT
(nF)+ t
on
To minimize this interval only a resistor has to be
connected between the DELAY and the V
REF
lim-
iting thus the duration to the internal propagation
delay ton.
Second step
Parameters: t
MON_DELAY
, V
CL
To protect the driven device from latch-up at turn-
on (IGBT) after the t
DELAY
time interval a second
externally programmable time interval
t
MON_DE-
LAY
(presettable using the same technique used
to set the t
DELAY
interval, see fig.4)
t
MON-DELAY
(
sec) = R
EXT
(K
) . C
EXT
(nF)
during the t
MON_DELAY
the voltage on the V
OUT1)
is limited to the V
CL
level. To program this value
an appropriate voltage drop has to be imposed,
by mean of a resistive voltage divider, at the
CLAMP_PROG pin according to the following for-
mula:
100nF
LOGIC
V
SS
(**)
OUT2
OUT1
V
POS
D94IN116B
V
REF
MON DELAY
CLAMP_PROG
COM
V
H.V.
DFW
LOAD
1.2
5.6
V
G
ON_SENSE
V
CE
INPUT
V
in
V
REF
12K
2.2K
100nF
(*)
V
REF
1nF
47K
ON_LEV_PROG
DELAY
V
REF
100pF
4.7K
V
REF
12K
12K
100nF
(*)
POSITIVE
SUPPLY
100
F-35V
100
F-10V
NEGATIVE
SUPPLY
100nF
SELECT
V
CC
NOTES:
(*) The capacitor is required if the pin is left floating.
(**) If the negative supply is not used, the V
SS
pin must be connected to the COM pin as close as possible to the IC.
Figure 4. Gate driving waveforms test circuit.
L6353
7/11
V
CLAMP_PROG
=
V
CL
6
with
7V < V
CL
<11V
Leaving the CLAMP_PROG pin floating the V
CL
level is set to 9V. If the pin is grounded the func-
tion is inhibited (i.e. no intermediate step during
the firing).
Third step
Parameter: V
ONth
At the end of the t
MON_DELAY
the gate of the
driven device is pulled toward the V
POS
level in
order to ensure an appropriate drive to minimize
the power losses. The external power device is
considered in overload whenever the voltage on
its output, sensed via the V
ON_SENSE
pin, is above
V
ONth
. The comparison value is programmable
setting at a certain level, by means of a resistive
divider, the ON_LEV_PROG pin according to the
following formula:
V
ON_LEV_PROG
= V
ONth
. 0.17
with
5V < V
ONth
. < 15V
and
V
ONth
. < V
CC
-1V.
If the ON_LEV_PROG pin is left floating theV
ONth
.
level is set to 7.5V.
The overload status is signalled via the ALARM
pin, active LOW. To inhibite the V
ON
Monitor func-
tion, the V
SENSE
pins must be grounded.
THERMAL PROCEDURE
As the junction temperature raises, two different
events will take place. When the Over Tempera-
ture Threshold (T
th1
), set at 130
C is reached, the
ALARM output is activated (low level). If the tem-
perature keeps on raising, up to the Over Tem-
peratur Shutdown (T
th2
= 160
C Typ) the output
power device is turned off until the temperature
decrease. To prevent an oscillating behaviour
both the thresholds have a built-in hysteresis of
20
C.
UNDERVOLTAGE LOCK OUT
To avoid operation with non optimal drive of the
external power device, an Undervoltage Lockout
function is implemented. The OUT1 pin is forced
close to V
SS
until the V
CC
supply voltage has
reached the
Undervoltage Upper Threshold
(V
CCth2
) value. If the supply voltage falls below
the lower hysteresis value (i.e. V
CCth1
- V
CChys
)
the OUT1 will be again forced close to V
SS
. The
built-in hysteresis will thus avoid intermittent func-
tioning of the device at low supply voltage that
may have a superimposed ripple.
Vs
D94IN126B
Vccth
Vcchys
Undervoltage Comparator Hysteresis
L6353
8/11
DIP16
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.77
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
0.050
OUTLINE AND
MECHANICAL DATA
L6353
9/11
SO16 Narrow
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.75
0.069
a1
0.1
0.25
0.004
0.009
a2
1.6
0.063
b
0.35
0.46
0.014
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.020
c1
45
(typ.)
D (1)
9.8
10
0.386
0.394
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F (1)
3.8
4
0.150
0.157
G
4.6
5.3
0.181
0.209
L
0.4
1.27
0.016
0.050
M
0.62
0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8
(max.)
L6353
10/11
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parti es which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics Printed in Italy All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
L6353
11/11
PDF 
ZIP