CXD2408AR
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2408AR is an IC developed to generate
the timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits.
Features
EIA support
Electronic shutter function
Random trigger shutter function
Sync signal generator
Supports external synchronization
Supports non-interlaced operation
Base oscillation 1560fh (24.5454MHz)
Applications
Progressive Scan CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX074AK, ICX074AL
Absolute Maximum Ratings
Supply voltage
V
DD
V
SS
0.5 to +7.0
V
Input voltage
V
I
V
SS
0.5 to V
DD
+ 0.5 V
Output voltage
V
O
V
SS
0.5 to V
DD
+ 0.5 V
Operating temperature Topr
20 to +75
C
Storage temperature
Tstg
55 to +150
C
Recommended Operating Conditions
Supply voltage
V
DD
4.75 to 5.25
V
Operating temperature Topr
20 to +75
C
1
E96402A68
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin LQFP (Plastic)
2
CXD2408AR
Block Diagram
RG
XH1
XH2
XSHP
XSHD
XRS
XV1
XV2
XV3
XSG
XHHG1A
XHHG1B
XHHG2
XVOG
XVHOLD
TG
PULSE GENERATOR
OUTPUT CONTROL
V-CONTROL
V-DECODER
1/525
1/390
H-DECODER
COUNTER
DECODE
1/2
GATE
TEST CIRCUIT
GATE
CKI
OSCO
OSCI
TRIG
PS
ED0
ED1
ED2
SMD1
SMD2
TEST7
TEST6
TEST5
VRI
HRI
CL
CLD
O2FH
FLD
BLK
SYNC
HDO
VDO
HDI
VDI
EXT
REND
REVH
OCTL
RDM
RM
XCPDM
XCPOB
PBLK
ID
WEN
XSUB
24.5MHz
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22
23
24
25
26
27
28
29
30
40
39 38 37 36
35
34
33
41
42
43
44
45
46
47
TEST8
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
1
TEST4
32
TEST2
21
TEST1
20
NC
TEST3
31
3
CXD2408AR
Pin Configuration
TEST4
TEST3
XRS
XSHD
XSHP
XSG
XV1
XV2
V
DD
V
SS
XV3
TEST2
TEST1
XVHOLD
XVOG
XHHG2
CL
CLD
O2FH
NC
FLD
BLK
V
SS
V
DD
SYNC
HDI
VDI
HDO
VDO
HRI
VRI
CKI
OSCO
OSCI
PS
ED0
ED1
ED2
SMD1
V
SS
SMD2
TRIG
RG
XSUB
XH1
XH2
XHHG1A
XHHG1B
TEST8
WEN
ID
PBLK
XCPOB
XCPDM
RM
RDM
V
SS
OCTL
REVH
REND
EXT
TEST7
TEST6
TEST5
CXD2408AR (G/A)
2
3
4
5
6
7
8
9
10
11 12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38 37
36 35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
1
4
CXD2408AR
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
OSCO
OSCI
PS
ED0
ED1
ED2
SMD1
Vss
SMD2
TRIG
RG
XSUB
XH1
XH2
XHHG1A
XHHG1B
XHHG2
XVOG
XVHOLD
TEST1
TEST2
XV3
Vss
V
DD
XV2
XV1
XSG
XSHP
XSHD
XRS
TEST3
TEST4
TEST5
TEST6
TEST7
O
I
I
I
I
I
I
--
I
I
O
O
O
O
O
O
O
O
O
O
O
O
--
--
O
O
O
O
O
O
O
O
O
O
I
Inverter output for oscillation.
Inverter input for oscillation.
Switching for electronic shutter speed input method. (With pull-down resistor)
Low: Parallel input, High: Serial input
Shutter speed setting. Strobe input for serial mode. (With pull-up resistor)
Shutter speed setting. Clock input for serial mode. (With pull-up resistor)
Shutter speed setting. Data input for serial mode. (With pull-up resistor)
Shutter mode setting. (With pull-up resistor)
GND
Shutter mode setting. (With pull-up resistor)
Trigger input for random trigger shutter.
Reset gate pulse output.
CCD discharge pulse output.
Clock output for CCD horizontal register drive.
Clock output for CCD horizontal register drive.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer from CCD vertical register to CCD horizontal register.
Clock output for adjusting timing of transfer to CCD horizontal register.
Test output. Normally open.
Test output. Normally open.
Clock output for CCD vertical register drive.
GND
Power supply.
Clock output for CCD vertical register drive.
Clock output for CCD vertical register drive.
CCD sensor charge readout pulse output.
Precharge level sample-and-hold pulse.
Data sample-and-hold pulse.
Sample-and-hold pulse.
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test input. Set at Low in normal operation. (With pull-down resistor)
Symbol
I/O
Description
5
CXD2408AR
Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
EXT
REND
REVH
OCTL
Vss
RDM
RM
XCPDM
XCPOB
PBLK
ID
WEN
TEST8
CL
CLD
O2FH
NC
FLD
BLK
Vss
V
DD
SYNC
HDI
VDI
HDO
VDO
HRI
VRI
CKI
I
I
I
I
--
I
I
O
O
O
O
O
I
O
O
O
--
O
O
--
--
O
I
I
O
O
I
I
I
Internal synchronization/external synchronization switching. (With pull-down resistor)
Low: Internal synchronization, High: External synchronization
Normal reset/direct reset switching. (With pull-down resistor)
Low: Normal reset, High: Direct reset
V reset/HV reset switching. (With pull-down resistor)
Low: V reset, High: HV reset
O2FH output control. (With pull-down resistor)
Low: No output, High: Output
GND
Normal operation/random trigger shutter switching. (With pull-down resistor)
Low: Normal operation, High: Random trigger shutter
Switching for output mode. (With pull-down resistor)
Low: Non-interlaced, High: Interlaced
Clamp pulse output.
Clamp pulse output.
Blanking cleaning pulse output.
Line identification output.
Write enable output.
Test input. (With pull-down resistor)
fck clock output. (0)
fck clock output. (180)
2 fH output.
Field pulse output.
Composite blanking output.
GND
Power supply.
Composite sync output.
Horizontal sync signal input.
Vertical sync signal input.
Horizontal sync signal output.
Vertical sync signal output.
Horizontal reset signal input.
Vertical reset signal input.
2 fck clock input.
Symbol
I/O
Description
6
CXD2408AR
Electrical Characteristics
DC Characteristics
(V
DD
= 4.75 to 5.25V, Topr = 20 to +75C)
Item
Supply voltage
Input voltage 1
(Input pins other than those below)
Input voltage 2
(Pins 7, 9, 10, 58, 59, 62, 63, and 64)
Output voltage 1
(Output pins other than those below)
Output voltage 2 (Pins 28, 29, 30,
31, 32, 33, 34, 49 and 50)
Output voltage 3
(Pins 11, 13, and 14)
Output voltage 4
(Pin 1)
Feedback resistor
Pull-up resistor
Pull-down resistor
Current consumption
V
DD
V
IH1
V
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
OH4
V
OL4
R
FB
R
PU
R
PD
I
DD
I
OH
= 2mA
I
OL
= 4mA
I
OH
= 4mA
I
OL
= 8mA
I
OH
= 12mA
I
OL
= 12mA
I
OH
= 12mA
I
OL
= 12mA
V
IN
= Vss or V
DD
V
IL
= 0V
V
IN
= V
DD
V
DD
= 5V
ICX074AL in normal
operating state
4.75
0.7V
DD
0.7V
DD
0.8
0.8
V
DD
0.8
V
DD
/2
250k
5.0
1M
50k
50k
35
5.25
0.3V
DD
0.3V
DD
0.4
0.4
0.4
V
DD
/2
2.5M
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
Symbol
Conditions
Min.
Typ.
Max.
Unit
I/O Pin Capacitances
(V
DD
= V
I
= 0V, f
M
= 1MHz)
Item
Input pin capacitance
Output pin capacitance
C
IN
C
OUT
--
--
--
--
9
11
pF
pF
Symbol
Min.
Typ.
Max.
Unit
7
CXD2408AR
AC Characteristics
1) Phase characteristics of XH1, RG, XSHP, XSHD, XRS, CL, and CLD
CK
XH1
RG
XSHP
XSHD
XRS
CL
CLD
tCK
Vpp/2
0.7V
DD
0.3V
DD
0.3V
DD
0.7V
DD
0.3V
DD
0.3V
DD
0.3V
DD
0.3V
DD
0.3V
DD
0.7V
DD
0.7V
DD
0.7V
DD
0.7V
DD
0.7V
DD
tpd1
tpd2
tpd3
tpd4
tpd5
tpd13
tpd11
tpd9
tpd7
tpd8
tpd6
tpd14
tpd12
tpd10
Symbol
t
CK
t
pd1
t
pd2
t
pd3
t
pd4
t
pd5
t
pd6
t
pd7
t
pd8
t
pd9
t
pd10
t
pd11
t
pd12
t
pd13
t
pd14
CK cycle
XH1 rising delay, activated by the falling edge of CK
XH1 falling delay, activated by the falling edge of CK
RG falling delay, activated by the rising edge of CK
RG rising delay, activated by the falling edge of CK
XSHP falling delay, activated by the rising edge of CK
XSHP rising delay, activated by the falling edge of CK
XSHD falling delay, activated by the rising edge of CK
XSHD rising delay, activated by the falling edge of CK
XRS falling delay, activated by the falling edge of CK
XRS rising delay, activated by the rising edge of CK
CL falling delay, activated by the rising edge of CK
CL rising delay, activated by the rising edge of CK
CLD falling delay, activated by the rising edge of CK
CLD rising delay, activated by the falling edge of CK
41
28
29
27
33
36
30
36
29
34
28
15
17
30
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Definition
Typ.
Unit
(V
DD
= 5.0V, Topr = 25C, Load capacity of CL and CLD = 30pF, Load capacity of XH1, XSHP, XSHD, XRS, and RG = 10pF)
8
CXD2408AR
XH1
RG
0.9V
DD
0.1V
DD
tfH1
trH1
trRG
tfRG
0.9V
DD
0.1V
DD
Symbol
t
rH1
t
fH1
t
rRG
t
fRG
XH1 rise time
XH1 fall time
RG rise time
RG fall time
2
2
2
2
ns
ns
ns
ns
Definition
Typ.
Unit
(V
DD
= 5.0V, Topr = 25C, Load capacity of XH1 = 10pF, Load capacity of RG = 10pF)
Waveform Characteristics of XH1 and RG
9
CXD2408AR
VRI
HDO
VDO
VDO
f
H
f
H
L: ODD H: EVEN
tp1
tp2
tp3
tp4
tp5
ODD
EVEN
259H
259H
2
1
1
2
Symbol
t
p1
t
p2
t
p3
t
p4
t
p5
Range of resetting to ODD
Range of resetting to EVEN
Range of resetting to ODD
Prohibited area
Prohibited area
21.9
31.6
9.7
200
200
s
s
s
ns
ns
Definition
Specified value
Unit
In the normal reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of
the vertical reset signal as shown in the figure below.
Field identification
10
CXD2408AR
VRI
HDO
VDO
VDO
f
H
f
H
L: ODD H: EVEN
tp1
tp2
tp3
tp4
tp5
ODD
EVEN
1
2
2
1
Symbol
t
p1
t
p2
t
p3
t
p4
t
p5
Range of resetting to ODD
Range of resetting to EVEN
Range of resetting to ODD
Prohibited area
Prohibited area
21.9
31.6
--
200
200
s
s
s
ns
ns
Definition
Specified value
Unit
In the direct reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the
vertical reset signal as shown in the figure below.
Field identification
In the direct reset mode, the cycle of HD can be arbitrary. Therefore,
t
p3 is not specified.
11
CXD2408AR
Description of Operation
1. Mode Control
Symbol
RM
RDM
PS
EXT
REND
REVH
42
41
3
36
37
38
1/30s non-interlaced
Normal operation
Parallel
Internal synchronization
Normal reset
V reset
1/60s interlaced
Random trigger shutter
Serial
External synchronization
Direct reset
HV reset
Electronic shutter speed input method
Pin No.
L
H
Remarks
2. Mode Relationships
RM
L
1/30s non-interlaced
L
Internal synchronization
L
H
Normal
operation
Random
trigger
shutter
Normal operation
H
Direct reset
L
Normal
reset
External synchronization
H
H
1/60s interlaced
L
Internal synchronization
L
H
Normal
operation
Random
trigger
shutter
Normal operation
L
V
reset
H
HV
reset
External synchronization
H
EXT
RDM
REND
REVH
: Disabled
Direct reset
L
H
V
reset
HV
reset
12
CXD2408AR
3. Electronic Shutter
<Shutter Modes>
SMD1
SMD2
L
L
Flickerless: Eliminates fluorescent frequency-induced flicker.
L
H
High-speed shutter: Shutter speed faster than 1/60
H
L
Low-speed shutter: Shutter speed slower than 1/60
H
H
No shutter operation
<Shutter Mode and Speed Setting Method>
PS = Low : Parallel input; set by ED0 to ED2, SMD1, and SMD2.
PS = High : Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin.
3-1. Parallel input
Shutter Speed Compatibility Chart
Mode
OFF
Flickerless
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
Shutter off
1/100 (s)
1/60 (s)
1/125 (s)
1/250 (s)
1/500 (s)
1/1000 (s)
1/2000 (s)
1/4000 (s)
1/10000 (s)
2FLD
4FLD
6FLD
8FLD
10FLD
12FLD
14FLD
16FLD
High-speed
shutter
Low-speed
shutter
PS
SMD1
SMD2
ED0
ED1
ED2
Shutter speed
Shutter speed is 1/30s in 1/30s mode, and 1/60s in 1/60s mode.
13
CXD2408AR
3-2. Serial input
For serial input (PS = High), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and
SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins
is invalid.
SMD1 SMD2
Dummy
D0
D1
D2
D3
D4
D5
D6
D7
D8
ED1 (CLK)
ED2 (DATA)
ED0 (STB)
ED2 data is latched to the register at the rise of ED1, and transferred to the within at the rise of ED0.
AC Characteristics
ED2
ED1
ED0
ts2
th2
tw1
ts1
tw0
ts0
Symbol
Definition
t
s2
t
h2
t
s1
t
w0
t
s0
t
w1
ED2 set-up time, activated by the falling edge of ED1
ED2 hold time, activated by the rising edge of ED1
ED1 rising set-up time, activated by the rising edge of ED0
ED0 pulse width
ED0 rising set-up time, activated by the rising edge of ED1
ED1 pulse width (serial input)
20ns
20ns
20ns
20ns
20ns
20ns
--
--
--
50s
--
--
Min.
Max.
14
CXD2408AR
3-3. Shutter speed calculation formula
High-speed shutter
T = [262
10
(1FF
16
L
16
)]
63.56 + 34.78 (s)
(
L
16
= Load value)
Load value
0FA
16
0FC
16
100
16
108
16
118
16
137
16
176
16
196
16
1/10000
1/4000
1/2000
1/1000
1/500
1/250
1/125
1/100
1/10169
1/4435
1/2085
1/1012
1/499
1/252
1/125
1/100
Shutter speed
Calculated value
Low-speed shutter
N = 2
(1FF
16
L
16
) FLD
However, the load value of FF
16
cannot be used .
Load value
1FE
16
1FD
16
:
101
16
100
16
2
4
:
508
510
Shutter speed (FLD)
In case of starting with serial input setting (PS = H), be sure to transfer shutter speed data in the range of
specification after power is turned on, and then use it..
15
CXD2408AR
4. Random Trigger Shutter
The random trigger shutter is different from the conventional electronic shutter in that the exposure beginning
can be freely set. The exposure period (shutter speed) can be set as with the conventional electronic shutter.
In this mode, XSUB rises for each 1H, and the charge stored in the sensor is discharged. Because the V clock
(XV1 to XV3) is continuously operating, any unneeded charge in the vertical CCD is eliminated.
XSG pulse is stopped until the external trigger is detected. The image cannot be monitored until the external
trigger is detected and the signal is read out.
When an external trigger is input in this state, HD is forcibly reset when the trigger falls, and XSUB falls once to
clear the charge and then halts. XV1 to XV3, XCPDM, XCPOB, and PBLK are reset with HD. From this point,
exposure begins, and after the preset exposure period has passed, the XSG pulse falls, the charge is
transferred from the sensor to the vertical CCD, and exposure ends. The XSG pulse falls with the time set as
in conventional electronic shutters, regardless of VD. Because HD is reset, the exposure period is accurate in
1H units. The WEN pulse is generated synchronously with the XSG pulse. As the WEN pulse specifies the
signal start, it can be used as the sync signal for writing image data into the frame memory.
In the random trigger shutter mode, V-direction functions of a sync signal generator are halted. As a result,
sync signals VD and FLD are also halted.
HD reset
XSUB reset
Shutter speed
TRIG
HD
XSUB
XV1
XV2
XV3
WEN
XSG
16
CXD2408AR
5. External Synchronization - Reset
HD and VD are reset to synchronize with the external sync signal.
Resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same.
There are two reset inputs: HRI and VRI. When their falling edge is detected, resetting is carried out. The
CXD2408AR has two reset modes: normal reset and direct reset. Details of the reset modes are described in
the following pages.
In the 1/30s non-interlaced readout mode, the normal reset mode is not supported, and although the direct
reset mode is supported, the field is not identified.
17
CXD2408AR
57.1 to 57.2s (701 to 702 bit)
Reset
6.3 to 6.37s
HRI
HD OUT
H reset
HRI
HDO
VRI
VDO
HRI
HDO
VRI
VDO
9H
259H
9H
259H
FIELD.O
FIELD.E
FIELD.O
FIELD.E
5-1. Normal reset
In the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from
that time. Only the mode which resets both HD and VD (HV reset) is supported.
When the H reset signal HRI is continuously with an H cycle, resetting is triggered at the first falling edge, and
after that point no resets are triggered at edges unless HD after resetting exceeds 2bits (163ns) on the internal
clock. In other words, the HRI input jitter is absorbed when it is up to 163 ns. The HRI minimum reset pulse
width is 0.3s.
In the V direction, counting begins from VRI fall, and V is reset to cause VDO to fall after 262.5 3.5 = 259H.
The VRI minimum reset pulse width is 2H.
Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification
timing is shown in Electrical Characteristics (Field identification).
18
CXD2408AR
5-2. Direct reset
In the direct reset mode, when the reset signal is input for resetting, a sync signal is output, but there is no
continuous output.
There are two direct reset modes: one to direct reset VD only (V reset), and one to reset both HD and VD (HV
reset). (However, note that even for V reset, the HRI signal is acceptable and the reset timing is the same as in
normal reset mode.) In both modes, the VD reset timing is the same.
When the external input V reset signal VRI fall is detected, a judgment is made as to ODD or EVEN. If ODD, V
is reset to cause VDO to fall simultaneously with HD fall, and if EVEN, V is reset to cause VDO to fall
simultaneously in the middle of HD. VRI requires a minimum pulse width of 2H.
H direct reset detects the fall of H reset signal HRI, and resets H so that HDO falls at the next CL falling edge.
The minimum HRI reset pulse width is 0.3s.
Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification
timing is shown in Electrical Characteristics (Field identification).
5-2-1. V reset
HRI
HDO
VRI
VDO
HRI
HDO
VRI
VDO
9H
9H
FIELD.O
FIELD.E
FIELD.O
FIELD.E
19
CXD2408AR
5-2-2. HV reset (1/60s interlaced readout mode)
HDO
HRI
VDO
VRI
XSG
ID
HDO
HRI
VDO
VRI
XSG
ID
HDO
FIELD.O
FIELD.E
CL
HRI
9H
9H
FIELD.E
FIELD.O
20
CXD2408AR
5-2-3. HV reset (1/30s non-interlaced readout mode)
HDO
HRI
VDO
VRI
XSG
ID
HDO
HRI
VDO
VRI
XSG
ID
9H
HDO
CL
HRI
9H
21
CXD2408AR
Timing Chart (1) <Vertical direction> 1/60s interlaced readout (RM = High)
1
5
FLD
VDO
XV1
XV2
XV3
OUT1
OUT2
XSG
XVHOLD
XVOG
XHHG1A
XHHG1B
XHHG2
PBLK
XCPOB
XCPDM
ID
WEN
HDO
BLK
493
494
1
2
3
4
5
6
7
8
2 4
6 8 10 12 14 16
1
3
5
7 9
11
13
525
493
494
3
7
1
5
3
7 9
13
11
15
2
6
4
8
2
6
4
8 10
14
12
16
270
275
280
285
15
10
11
12 13
14
15 16
17
18 19
20
1
2 3
4
5 6
7
8 9
260
261 262
263
264 265
22
CXD2408AR
Timing Chart (2) <Vertical direction> 1/30s non-interlaced readout (RM = Low)
1
2
3 4
5
6
7
8
1
2
3 4
FLD
VDO
BLK
HDO
XV1
XV2
XV3
OUT1
XSG
XVHOLD
XVOG
XHHG1A
XHHG1B
XHHG2
PBLK
XCPOB
XCPDM
ID
WEN
493
1
2
3 4 5 6 7 8 1 2 3
494
493
494
525
525
1
2
3 4
5
6 7
8
9
10
11
12
13 14
15
16 17
18
19 20
21
22 23
24
25 26
1
2
3 4
5
6 7
8
9
10
11
12 13
14
15 16
17
18 19
20
21 22
23
24 25
26
23
CXD2408AR
Timing Chart (3) <Horizontal direction> 1/60s interlaced readout (RM = High)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
BLK/HD
CL
XHHG1A
XV1
XV2
XV3
XVHOLD
XVOG
XHHG1B
XHHG2
XH1
XH2
RG
XSHP
XSHD
XSUB
PBLK
XCPOB
XCPDM
ID
WEN
OPB (31 bits)
35
53
41
47
47
71
59
77
89
95
65
83
65
83
37
52
78
89
95
35
35
63
59
77
77
95
47
76
101
101
100
75
56
72
95
115
93
93
35
31
13
Dummy (16 b
i
t
s
)
OPB (2 bits)
78
132
69
114
105
58
24
CXD2408AR
Timing Chart (4) <Horizontal direction> 1/30s non-interlaced readout (RM = Low)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
BLK/HD
CL
XHHG1A
XV1
XV2
XV3
XVHOLD
XVOG
XHHG1B
XHHG2
XH1
XH2
RG
XSHP
XSHD
XSUB
PBLK
XCPOB
XCPDM
ID
WEN
OPB (31 bits)
35
47
59
77
89
65
35
35
95
101
100
72
95
115
105
93
93
35
31
13
Dummy (16 bits)
OPB (2 bits)
89
59
65
35
78
132
114
25
CXD2408AR
Timing Chart (5) <V2/V3 simultaneous readout timing> 1/60s interlaced (RM = High)
HD
XV1
XV2
XV3
XSG
XV1
XV2
XV3
XSG
ODD Field
EVEN Field
42.4s (520 bits)
16.1s (198 bits)
2.53s (31 bits)
2.94s (36 bits)
2.53s (31 bits)
Timing Chart (6) <V2/V3 simultaneous readout timing> 1/30s non-interlaced (RM = Low)
HD
XV1
XV2
XV3
XSG
ODD Field
42.4s (520 bits)
16.1s (198 bits)
2.53s (31 bits)
2.94s (36 bits)
2.53s (31 bits)
26
CXD2408AR
Timing Chart (7) <High-speed phase>
HD
CKI
CL
XH1
XH2
RG
XSHP
XSHD
XRS
CLD
27
CXD2408AR
Timing Chart (8) <SG vertical direction>
HDO
VDO
SYNC
BLK
FLD
Field E
Field O
O : ODD
E : EVEN
9H
20H
HDO
VDO
SYNC
BLK
FLD
9H
20H
Field E
Field O
28
CXD2408AR
Timing Chart (9) <SG horizontal direction>
HDO
BLK
HSYNC
EQ
VSYNC
VDO
FLD
2FH
FH
ODD
EVEN
6.36s (78 bits)
4.89s (60 bits)
2.45s (30 bits)
26.89s (330 bits)
4.89s (60 bits)
63.56s (780 bits)
1/2H 31.78s
(390 bits)
9.86s
(121 bits)
11.82s
(145 bits)
10.14s
(124 bits)
9.78s
(120 bits)
22.00s (27 bits)
1.47s (18 bits)
10.76s (132 bits)
29
CXD2408AR
CXD2408AR
12p
20p
1000p
0.01
10/10V
2.2K
47p
47p
2.2K
47p
2.2K
47p
2.2K
47p
2.2K
0.01
10/10V
47p
2.2K
47p
2.2K
47p
2.2K
74HC04
CXD1250M
VSUB ADJ.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
ICX074AK/AL
CXA1690Q
CXA1690Q
CXD2311AR
CXD2311AR
N.C.
N.C.
47p
2.2K
47p
2.2K
N.C.
N.C.
To MEMORY CONTROLLER
N.C.
CCD OUT1
CCD OUT2
ANALOG OUT1
ANALOG OUT2
DIGITAL OUT1
(10bit)
DIGITAL OUT2
(10bit)
13
14
15
21
22
24
22
22
13
14
15
21
24
22
+5V
Input only for random trigger shutter mode.
CXD1268M
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
1
Application Circuit (1/60s interlaced, internal synchronization, normal continuous operation)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo
r
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same
.
30
CXD2408AR
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
12.0
0.2
10.0
0.1
(0.22)
b
1
16
17
32
33
48
49
64
0.1
0.1
0.5
0.2
0
to 10
64PIN LQFP (PLASTIC)
LQFP-64P-L01
LQFP064-P-1010
0.3g
DETAIL A
0.5
0.2
(1
1.0)
A
1.5 0.1
+ 0.2
0.1
SOLDER/PALLADIUM
NOTE: Dimension "
" does not include mold protrusion.
0.13 M
0.5
b = 0.18 0.03
( 0.18 )
(0.127)
+ 0.08
0.127
0.02
+ 0.05
DETAIL B : SOLDER
b = 0.18
0.03
0.125
0.04
DETAIL B : PALLADIUM
Sony Corporation
PDF 
ZIP