ST
Sitronix
ST2100
PRELIMINARY
8 BIT Microcontroller with 2M bytes ROM
Notice: This is not a final specification. Some parameters are subject to change.
Ver 2.6c
1/49
2002-Jul-25
1
1
.
.
F
F
E
E
A
A
T
T
U
U
R
R
E
E
S
S
8-bit static pipeline CPU
ROM: 2M x 8 bits
RAM: 4K x 8 bits
External memory control up to 8M x 8 bits
Operation voltage : 2.4V ~ 6V
24 CMOS Bi-directional bit programmable I/O pins
Hardware de-bounce option for input port
Bit programmable PULL-UP for input port
Timer/Counter
:
- Two 8-bit timer/16-bit event counter
- One 8-bit BASE timer
Six powerful interrupt sources :
- External interrupt (edge trigger)
- TIMER0 interrupt
- TIMER1 interrupt
- BASE timer interrupt
- PORTA[7~0] interrupt (transition trigger)
- DAC reload interrupt
128-level
deep
stack
Dual clock source :
- OSCX: Crystal oscillator 32.768K Hz
- OSCI: RC oscillator 500K ~ 4M Hz or
OSCI,XIO: Resonator 500K ~ 4M Hz (code option)
Built-in oscillator with warm-up timer
DMA control LCD driver area :
-
5376 (48x112) dots
-
4096 (32X128) dots
Programmable Sound Generator (PSG) includes :
- Dual Tone generator (including Noise generator)
- 16 level volume sound effect generator
- Digital DAC for speech / tone
Three power down modes :
- WAI0 mode
- WAI1 mode
- STP mode
2
2
.
.
G
G
E
E
N
N
E
E
R
R
A
A
L
L
D
D
E
E
S
S
C
C
R
R
I
I
P
P
T
T
I
I
O
O
N
N
The ST2100 is a single chip micro-controller designed with
CMOS silicon gate technology. This single chip micro-controller
is useful for business equipment and other consumer
applications. It integrates with 8-bit CPU core, SRAM, timer,
LCD driver, I/O port and mask program ROM. This chip built-in a
dual-oscillator to enhance the chip performance.
Sitronix ST2100
Ver 2.6c
4/49
2002-Jul-25
Pad Description
Pin No.
Designation
I/O
Description
13
RESET
I
Pad reset input (active low)
16,29,53,66 GND P
Ground
Input and chip sub-strate
17-24
PORTA[0-7]
I/O
Programmable I/O, Transition Interrupt(edge active), INTX Interrupt , Timer
Prescaler PRE16 clock source
25-28,30-33
PORTB [0-7]
I/O
Bit programmable I/O,PSG output, DAC output
34-41
PORTC [0-7]
I/O
Bit programmable I/O
55-64,67-78
A[0-21]
O
Address bus for expand memory
65
A[22]/CSB0
O
Address bus for expand memory / Expand memory chip select signal
45-52
D[0-7]
I/O
Data bus for expand memory
44
R/W
O
Read or write signal for expand memory
54
CSB/CSB1
O
Expand memory chip select signal
43
EXT_MEM
O
External memory enable/disable control signal
11 VDD
P
Power
supply
pin
14,15
OSCXO, OSCXI
I/O
OSCX I/O pin. For 32768Hz crystal used.
10
OSCI
I
RC oscillator pin, had to be connected to external resistor
4
TEST
I
Test pin for chip test, normal to NC.
1
FLM
O
First line mark for common signal(to LCD driver ST2101)
2
LOAD
O
Load data into Segment or common driver's data latch (to LCD driver ST2101)
8
AC
O
LCD alternating signal (connect to LCD driver ST2101)
3
POFFB
O
Control the power generator of voltage pumping circuit (to LCD driver ST2101)
9 XIO
O
OSCI,XIO
for
resonator
500K ~ 4M Hz (code option)
6
CP
O
Shift clock pulse for segment driver (to LCD driver ST2101)
5
DATAOUT
O
Output serial data for segment driver (to LCD driver ST2101)
7
BLANKB
O
LCD display can be turn off directly by external control. When BLANKB is low, the
LCD display automatically set to blank state (to LCD driver ST2101).
42
EXT_MODE
I
Select {CSB,A[22]} or {CSB0,CSB1}
12 VDD
P
Power
supply
pin
Legend: I = input, O = output, I/O = input/output, P = power.
Sitronix ST2100
Ver 2.6c
5/49
2002-Jul-25
5
5
.
.
C
C
P
P
U
U
7
0
A
7
0
Y
7
0
X
7
0
PCH PCL
8 7
0
1 S
Accumulator A
Index Register Y
Index Register X
Program Counter PC
Stack Pointer S
CPU REGISTER MODEL
5.1 Accumulator
(A)
The accumulator is a general purpose 8-bit register which stores
the results of most arithmetic and logic operations. In addition,
the accumulator usually contains one of the two data words
used in these operations.
5.2 Index Registers (X,Y)
There are two 8-bit Index Registers (X and Y) which may be
used to count program steps or to provide and index value to be
used in generating an effective address. When executing an
instruction which specifies indexed addressing, the CPU fetches
the OP code and the base address, and modifies the address by
adding the index register to it prior to performing the desired
operation. Pre or post-indexing of indirect addresses is possible.
5.3 Stack Pointer (S)
The stack Pointer is an 8-bit register which is used to control the
addressing of the variable-length stack. It's range from 100H to
1FFH total for 256 bytes (128 level deep). The stack pointer is
automatically increment and decrement under control of the
microprocessor to perform stack manipulations under direction
of either the program or interrupts (IRQ). The stack allows simple
implementation of nested subroutines and multiple level
interrupts. The stack pointer is initialized by the user's software.
5.4 Program Counter (PC)
The 16-bit Program Counter register provides the address which
step the microprocessor through sequential program
instructions. Each time the microprocessor fetches and
instruction from program memory, the lower byte of the program
counter (PCL) is placed on the low-order bits of the address bus
and the higher byte of the program counter (PCH) is placed on
the high-order 8 bits. The counter is increment each time an
instruction or data is fetched from program memory.
5.5 Status Register (P)
The 8-bit Processor Status Register contains seven status flags.
Some of the flags are controlled by the program, others may be
controlled both by the program and the CPU. The instruction set
contains a member of conditional branch instructions which are
designed to allow testing of these flags. Refer to TABLE 5-1:
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