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Электронный компонент: LZ2523

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1
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
DESCRIPTION
The LZ2523 is a 1/5-type (3.6 mm) solid-state
image sensor that consists of PN photo-diodes
and CCDs (charge-coupled devices). With
approximately 320 000 pixels (542 horizontal x 582
vertical), the sensor provides a stable high-resolution
color image.
FEATURES
Number of effective pixels : 512 (H) x 582 (V)
Number of optical black pixels
Horizontal : 2 front and 28 rear
Pixel pitch : 5.8 m (H) x 3.8 m (V)
Mg, G, Cy, and Ye complementary color filters
Low fixed-pattern noise and lag
No burn-in and no image distortion
Blooming suppression structure
Built-in output amplifier
Built-in overflow drain voltage circuit and reset
gate voltage circuit
Horizontal shift register clock voltage : 3.6 V (TYP.)
Variable electronic shutter (1/50 to 1/10 000 s)
Compatible with PAL standard
Package :
14-pin half-pitch WDIP [Plastic]
(WDIP014-P-0400A)
Row space : 10.16 mm
PIN CONNECTIONS
PRECAUTIONS
The exit pupil position of lens should be more
than 25 mm from the top surface of the CCD.
Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
LZ2523
1/5-type Color CCD Area Sensor
with 320 k Pixels
LZ2523
1
OD
2
RS
3
NC
1
4
OS
5
NC
2
6
H2
7
H1
14
13
12
11
10
9
8
GND
V4
V3
V2
V1
PW
OFD
14-PIN HALF-PITCH WDIP
TOP VIEW
(WDIP014-P-0400A)
LZ2523
2
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25 C)
SYMBOL
PIN NAME
OD
Output transistor drain
OS
Output signals
RS
Reset transistor clock
V1
,
V2
,
V3
,
V4
Vertical shift register clock
H1
,
H2
Horizontal shift register clock
PW
P-well
GND
Ground
NC
1
, NC
2
No connection
PARAMETER
SYMBOL
RATING
UNIT
Output transistor drain voltage
V
OD
0 to +18
V
Reset gate clock voltage
V
RS
Internal output
V
Vertical shift register clock voltage
V
V
11.5 to +17.5
V
Horizontal shift register clock voltage
V
H
0.3 to +12
V
Voltage difference between P-well and vertical clock
V
PW
-V
V
29 to 0
V
Storage temperature
T
STG
40 to +85
C
Ambient operating temperature
T
OPR
20 to +70
C
2
NOTE
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect V
OD
to GND. Overflow drain clock is
applied below 27 Vp-p.
2. Do not connect to DC voltage directly. When
RS
is connected to GND, connect V
OD
to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 s, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 28 V.
Overflow drain
OFD
1
V
Internal output
V
OFD
Overflow drain voltage
3
V
0 to +15
V
V
-V
V
Voltage difference between vertical clocks
3
LZ2523
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Ambient operating temperature
T
OPR
25.0
C
Output transistor drain voltage
V
OD
14.55
15.0
15.45
V
NOTES :
Connect NC
1
and NC
2
to GND directly or through a capacitor larger than 0.047 F.
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.
2. V
PW
is set below V
VL
that is low level of vertical shift register clock, or is used with the same power supply that is connected
to V
L
of V driver IC.
* To apply power, first connect GND and then turn on V
OD
. After turning on V
OD
, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
1
V
24.5
22.5
V
OFD
Overflow drain clock
P-well voltage
V
PW
10.0
V
VL
V
2
Ground
GND
0.0
V
V
8.5
9.0
9.5
V
V1L
, V
V2L
V
V3L
, V
V4L
Vertical shift
register clock
LOW level
INTERMEDIATE level
HIGH level
V
V1I
, V
V2I
V
V3I
, V
V4I
V
V1H
, V
V3H
14.55
0.0
15.0
15.45
V
V
LOW level
Horizontal shift
register clock
V
H1L
, V
H2L
0.05
0.0
0.05
V
HIGH level
V
H1H
, V
H2H
3.3
3.6
5.5
V
1
V
5.5
5.0
4.5
V
RS
Reset gate clock
p-p level
Reset gate clock frequency
f
RS
9.66
MHz
Horizontal shift register clock frequency
f
H1
, f
H2
9.66
MHz
Vertical shift register clock frequency
f
V1
, f
V2
f
V3
, f
V4
15.63
kHz
p-p level
LZ2523
4
CHARACTERISTICS
(Drive method : Field accumulation)
(T
A
= +25 C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Standard output voltage
V
O
150
mV
2
Photo response non-uniformity
PRNU
15
%
3
Saturation output voltage
V
SAT
500
650
mV
4
Dark output voltage
V
DARK
0.5
3.0
mV
1, 5
Dark signal non-uniformity
DSNU
0.5
2.0
mV
1, 6
Sensitivity
R
145
200
mV
7
Smear ratio
SMR
80
70
dB
8
Image lag
AI
1.0
%
9
Blooming suppression ratio
ABL
1 000
10
Output transistor drain current
I
OD
4.0
8.0
mA
Output impedance
R
O
350
$
Vector breakup
7.0
, %
11
Line crawling
3.0
%
12
Luminance flicker
2.0
%
13
NOTES :
Within the recommended operating conditions of V
OD
,
V
OFD
of the internal output satisfies with ABL larger than
1 000 times exposure of the standard exposure conditions,
and V
SAT
larger than 500 mV.
1. T
A
= +60 C
2. The average output voltage under uniform illumination.
The standard exposure conditions are defined as when
Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT
is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions.
5. The average output voltage under non-exposure
conditions.
6. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
7. The average output voltage when a 1 000 lux light
source with a 90% reflector is imaged by a lens of F4,
f50 mm.
8. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
9. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
10. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
11. Observed with a vector scope when the color bar chart
is imaged under the standard exposure conditions.
12. The difference between the average output voltage of the
(Mg + Ye), (G + Cy) line and that of the (Mg + Cy), (G +
Ye) line under the standard exposure conditions.
13. The difference between the average output voltage of
the odd field and that of the even field under the
standard exposure conditions.
LZ2523
5
PIXEL STRUCTURE
,,
,,
,,
,,
,,
,,
yy
yy
yy
yy
yy
yy
,,,
,,,
,,,
,,,
,,,
,,,
yyy
yyy
yyy
yyy
yyy
yyy
512 (H) x 582 (V)
1 pin
OPTICAL BLACK
(2 PIXELS)
OPTICAL BLACK
(28 PIXELS)
COLOR FILTER ARRAY
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Mg
G
Mg
G
Mg
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Ye
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Mg
Ye
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Mg
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Ye
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Mg
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
(1, 582)
(512, 582)
(1, 1)
(512, 1)
2nd, 4th
field
1st, 3rd
field
LZ2523
6
TIMING CHART
580
+
581
582
1
+
2
3
+
4
5
+
6
7
+
8
OS
OFD
V4
V3
V2
V1
VD
HD
(1st, 3rd FIELD)
Shutter speed
1/2 000 s
VERTICAL TRANSFER TIMING
579
+
580
581
+
582
1
2
+
3
4
+
5
6
+
7
OS
OFD
V4
V3
V2
V1
VD
HD
(2nd, 4th FIELD)
623
311
318
332
625 1
6
22
20
OS
RS
H2
H1
HD
...512
OB (28)
OB (2)
OFD
V4
V3
V2
V1
HORIZONTAL TRANSFER TIMING
618, 1
60
29
49
39
54
24
34
64
62
72
59
OUTPUT (512) 1
LZ2523
7
V4
V3
V2
V1
HD
V4
V3
V2
V1
HD
(1st, 3rd FIELD)
(2nd, 4th FIELD)
READOUT TIMING
1
29
39
24
34
64
54
59
161
180
290
338
242
290
449
618, 1
60
29
39
54
64
34
59
49
49
60
1
29
39
24
34
64
54
59
161
180
290
338
242
290
618, 1
60
54
64
450
59
49
60
LZ2523
8
SYSTEM CONFIGURATION EXAMPLE
OD
OS
NC
1
OFD
PW
RS
H2
H1
GND
V4
V3
V2
V1
NC
2
V
3B
V
3A
V
1B
V
1A
V
Ma
V
H
V
4
V
2
V
L
V
Mb
POFD
NC
V
H
V
OD
V
4X
V
L
(V
PW
)
V
3X
V
2X
V
1X
VH
3AX
VH
1AX
+5 V
OFDX
H1
H2
RS
CCD
OUT
0.01 F
1 M$
V
OFDH
VH
3BX
OFDX
V
2X
V
1X
V
3X
V
DD
GND
V
4X
VH
3AX
VH
1BX
VH
1AX
+
+
1
2
3
4
5
6
7
8
12
24
23
22
21
20
19
18
17
13
11
14
10
15
9
16
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LR36685
LZ2523
100 $
270 pF
1 M$
0.1 F
(*1)
(*1)
+
+
(*1)
RS
, OFD :
Use the circuit parameter indicated in
this circuit example, and do not connect
to DC voltage directly.
PACKAGES FOR CCD AND CMOS DEVICES
9
( : Lid's size)
10.00
0.10
0.50
0.50
0.50
0.50
10.00
0.10
0.25
0.10
9.00
0.10
()
10.16
5.00
0.075
5.00
0.075
CCD
1
7
8
14
0.03
0.03
1.39
0.05
1.96
0.05
9.00
0.10
()
Package
Glass Lid
CCD
Rotation error of die : = 1.0
MAX.
Center of effective imaging area
and center of package
Cross section A-A'
3.50
0.30
1.27
0.25
2.55
0.10
0.30
TYP.
0.46
TYP.
P-1.27
TYP.
5.02
MAX.
3.35
0.10
A'
A
0.80
0.05
()
M
0.25
+0.5
0
PACKAGE
(Unit : mm)
14 WDIP (WDIP014-P-0400A)
PRECAUTIONS FOR CCD AREA SENSORS
PRECAUTIONS FOR CCD AREA SENSORS
1. Package Breakage
In order to prevent the package from being broken,
observe the following instructions :
1) The CCD is a precise optical component and
the package material is ceramic or plastic.
Therefore,
Take care not to drop the device when
mounting, handling, or transporting.
Avoid giving a shock to the package.
Especially when leads are fixed to the socket
or the circuit board, small shock could break
the package more easily than when the
package isn't fixed.
2) When applying force for mounting the device or
any other purposes, fix the leads between a
joint and a stand-off, so that no stress will be
given to the jointed part of the lead. In addition,
when applying force, do it at a point below the
stand-off part.
(In the case of ceramic packages)
The leads of the package are fixed with low
melting point glass, so stress added to a
lead could cause a crack in the low melting
point glass in the jointed part of the lead.
(In the case of plastic packages)
The leads of the package are fixed with
package body (plastic), so stress added to a
lead could cause a crack in the package
body (plastic) in the jointed part of the lead.
3) When mounting the package on the housing,
be sure that the package is not bent.
If a bent package is forced into place
between a hard plate or the like, the pack-
age may be broken.
4) If any damage or breakage occurs on the sur-
face of the glass cap, its characteristics could
deteriorate.
Therefore,
Do not hit the glass cap.
Do not give a shock large enough to cause
distortion.
Do not scrub or scratch the glass surface.
Even a soft cloth or applicator, if dry, could
cause dust to scratch the glass.
2. Electrostatic Damage
As compared with general MOS-LSI, CCD has
lower ESD. Therefore, take the following anti-static
measures when handling the CCD :
1) Always discharge static electricity by grounding
the human body and the instrument to be used.
To ground the human body, provide resistance
of about 1 M$ between the human body and
the ground to be on the safe side.
2) When directly handling the device with the
fingers, hold the part without leads and do not
touch any lead.
Glass cap
Package
Lead
Fixed
Stand-off
Fixed
Lead
Stand-off
Low melting point glass
10
PRECAUTIONS FOR CCD AREA SENSORS
3) To avoid generating static electricity,
a. do not scrub the glass surface with cloth or
plastic.
b. do not attach any tape or labels.
c. do not clean the glass surface with dust-
cleaning tape.
4) When storing or transporting the device, put it in
a container of conductive material.
3. Dust and Contamination
Dust or contamination on the glass surface could
deteriorate the output characteristics or cause a
scar. In order to minimize dust or contamination on
the glass surface, take the following precautions :
1) Handle the CCD in a clean environment such
as a cleaned booth. (The cleanliness level
should be, if possible, class 1 000 at least.)
2) Do not touch the glass surface with the fingers.
If dust or contamination gets on the glass
surface, the following cleaning method is
recommended :
Dust from static electricity should be blown
off with an ionized air blower. For anti-
electrostatic measures, however, ground all
the leads on the device before blowing off
the dust.
The contamination on the glass surface
should be wiped off with a clean applicator
soaked in Isopropyl alcohol. Wipe slowly and
gently in one direction only.
Frequently replace the applicator and do not
use the same applicator to clean more than
one device.
Note : In most cases, dust and contamination
are unavoidable, even before the device
is first used. It is, therefore, recommended
that the above procedures should be
taken to wipe out dust and contamination
before using the device.
4. Other
1) Soldering should be manually performed within
5 seconds at 350 C maximum at soldering iron.
2) Avoid using or storing the CCD at high tem-
perature or high humidity as it is a precise
optical component. Do not give a mechanical
shock to the CCD.
3) Do not expose the device to strong light. For
the color device, long exposure to strong light
will fade the color of the color filters.
11
PRECAUTIONS FOR CCD AREA SENSORS