K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Revision No

0.0

0.1

0.2

0.3

History

Initial issue

1. Explain how pointer operation works in detail.
2. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes
into Busy for maximum 5us.

1. Renamed the 17th pin from Vcc to LVD(Low Voltage Detect)
-The LVD is used to electrically detect the proper supply voltage.
By connecting this pin to Vss through a pull-down resister, it is pos-
sible to distinguish 3.3V product from 5V product. When 3.3V is
applied as Vcc to pins 12 and 22, a 'High' level can be detected
on the system side if the device is a 3.3V product, and 'Low' level
for 5V product.

1.Powerup sequence is added
Recovery time of minimum 1

s is required before internal circuit gets

ready for any command sequences

2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR1 value : 100ns --> 20ns

Draft Date

July 17th 2000

Nov. 20th 2000

Mar. 2th 2001

Sep. 7th 2001

Remark

Advanced
Information
Preliminary

Final

Document Title

SmartMedia

Card

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.

Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

High

~ 2.5V

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Revision No

0.4

History

1. Unified access timing parameter definition for multiple operating modes
- Changed AC characteristics (Before)

- AC characteristics (After)

. Deleted t

RSTO,

CSTO

and t

READID

/ Added

CLR,

CEA

Parameter

Symbol

Min

Max

Unit

ALE to RE Delay (ID read)

AR1

100

ALE to RE Delay (Read cycle)

AR2

100

RE Low to Status Output

RSTO

CE Low to Status Output

CSTO

RE access time(Read ID)

READID

Parameter

Symbol

Min

Max

Unit

ALE to RE Delay (ID read)

AR1

ALE to RE Delay (Read cycle)

AR2

CLE to RE Delay

CLR

CE Access Time

CEA

Draft Date

Sep. 7th 2001

Remark

Final

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

Note : For more detailed features and specifications including FAQ, please refer to Samsung Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

CLE

I/O

ALE

90h

00h

ECh

Address. 1cycle

Maker code

tCEA

tAR

tREA

tWHR

CLE

I/O

ALE

90h

00h

ECh

Address. 1cycle

Maker code

tCR

tAR

tREA

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

History

1. Eliminated the duplicated AC parameter.
- AC characteristics (Before)

. Replaced t

AR1,

AR2

with t

- AC characteristics (After)

Parameter

Symbol

Min

Max

Unit

ALE to RE Delay (ID read)

AR1

ALE to RE Delay (Read cycle)

AR2

CLE to RE Delay

CLR

CE Access Time

CEA

Parameter

Symbol

Min

Max

Unit

ALE to RE Delay

CLE to RE Delay

CLR

CE Access Time

CEA

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

Revision History

Revision No

0.5

Remark

Final

Draft Date

Feb. 9th 2002

CLE

I/O

70h

Status Output

tCLS

tCLH

tCS

tWP

tCH

tDS

tDH

tRSTO

tIR

tRHZ

tCHZ

tWHR

tCSTO

tCLS

CLE

I/O

70h

Status Output

tCLS

tCLH

tCS

tWP

tCH

tDS

tDH

tREA

tIR

tRHZ

tCHZ

tWHR

tCEA

tCLS

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

SmartMedia

Card

Using Nand flash memory, SmartMedia provides the most cost-
effective solution for the solid state mass storage market. A pro-
gram operation is implemented by the single page of 528 bytes
in typical 200

s and an erase operation is done by the single

block of 16K bytes (K9S6408V0X: 8K bytes) in typical 2ms.
Data in a page can be read out at 50ns cycle time per byte. The
I/O pins serve as ports for address and data inputs/outputs as
well as command inputs. The on-chip writing controller auto-
mates all program and erase functions including pulse repeti-
tion, where required, and internal verification and margining of
data. Even the write-intensive systems can take advantage of
the SmartMeida

s extended reliability of 100K program/erase

cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. (*Endurance varies according to its
density. please refer to Features). SmartMedia is an optimum
solution for data storage applications such as solid state file
storage, digital voice recorder, digital still camera and other por-
table applications requiring non-volatility.

GENERAL DESCRIPTION

FEATURES

·Single 2.7V~3.6V Supply
·Organization
- Memory Cell Array :
8MB(K9S6408V0X) : ( 8M + 256K)bit x 8bit
16MB(K9S2808V0X) : (16M + 512K)bit x 8bit
32MB(K9S5608V0X) : (32M + 1,024K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
·Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase
32MB, 16MB(K9S56/2808V0X) : (16K + 512)Byte
8MB (K9S6408V0X) : (8K + 256)Byte
·528-Byte Page Read Operation
- Random Access : 10

s(Max.)

* K9S6408V0B/A : 7

s(Max.)

* K9S6408V0C : 10

s(Max.)

- Serial Page Access : 50ns(Min.)
·Fast Write Cycle Time
- Program Time : 200

s(Typ.)

- Block Erase Time : 2ms(Typ.)
·Command/Address/Data Multiplexed I/O Port
·Hardware Data Protection
- Program/Erase Lockout During Power Transitions
·Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
* K9S6408V0X : 1Million Program/Erase Cycles
- Data Retention : 10 years
·Command Register Operation
·22pad SmartMedia

(SSFDC)

·Unique ID for Copyright Protection

SmartMedia

CARD(SSFDC)

NOTE : Connect all V

and V

pins of each device to common power supply outputs and do not leave V

or V

disconnected.

PIN DESCRIPTION

Pin Name

Pin Function

I/O0 ~ I/O7

Data Input/Outputs

CLE

Command Latch Enable

ALE

Address Latch Enable

Chip Enable

Read Enable

Write Enable

Write Protect

LVD

Low Voltage Detect

GND

Ground

R/B

Ready/Busy output

Power

Ground

N.C

No Connection

I/O

LVD

GND

R/B

I/O

ALE

CLE

22 PAD SmartMedia

ID 32MB

PIN DESCRIPTION

Device

Unique ID Support

K9S2808V0X
K9S5608V0X
K9S6408V0C

K9S6408V0A/M

The pin 17(LVD) is used to detect 5V or 3.3V product electrically. Please, refer to the SmartMedia Application note for detail.

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Figure 1. FUNCTIONAL BLOCK DIAGRAM

X-Buffers

Command

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

- A

Command

CE
RE
WE

I/0 0

I/0 7

CLE ALE

NAND Flash

ARRAY

Y-Gating

Page Register & S/A

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0X : 128M + 4M Bit

K9S6408V0X : 64M + 2M Bit

K9S5608V0X : 256M + 8M Bit

K9S2808V0X :

(512 + 16)Byte x 32,768

K9S6408V0X :

(512 + 16)Byte x 16,384

K9S5608V0X :

(512 + 16)Byte x 65,536

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

512B Byte

16 Byte

Figure 2. ARRAY ORGANIZATION

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
A

: K9S6408V0X should be designated up to A

, addresse A

23 to

must be set to "Low"

: K9S2808V0X should be designated up to A

, address A

must be set to "Low".

: K9S5608V0X should be designated up to A

* A

is set to "Low" or "High" by the 00h or 01h Command.

* The device ignores any additional input of address cycles than reguired.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

2nd Cycle

3rd Cycle

1st half Page Register
(=256 Bytes)

2nd half Page Register
(=256 Bytes)

Pages

512 Byte

8 bit

16 Byte

I/O 0 ~ I/O 7

Page Register

ARRAY ORGANIZATION

1 Page

1 Block

1 Device

K9S6408V0X

528 Byte

528 Bytes x 16 Pages

528 Byte x 16Pages x 1024 Blocks

K9S2808V0X

528Byte

528Bytes x 32 Pages

528Byte x 32Pages x 1024 Blocks

K9S5608V0X

528 Byte

528 Byte x 32 Pages

528Bytes x 32Pages x 2048 Blocks

Column Address
Row Address

(Page Address)

(8MB) : 1block=16pages
(16MB/32MB) : 1block=32pages

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

PRODUCT INTRODUCTION

The SmartMeida has the memory organization as following Table1. Spare sixteen columns are located from column address of 512
to 527. A 528-byte data register is connected to memory cell arrays and is accommodating data-transfer between the I/O buffers and
memory cell arrays during page read and page program operations. The memory array is made up of 16 cells that are serially con-
nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two 16
cell memory array. The array organization is shown in Figure 2. The program and the read operations are executed on a page basis,
while the erase operation is executed on a block basis.

The SmartMedia has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows system upgrade to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except
for Block Erase and Page Program commands which require two cycles: one cycle for a setup and another for an execution. The
physical space of the SmartMedia varies according to its density and from 8MB to 32MB SmartMedia require three cycles for byte-
level addressing; column address, row address, in that order. Page Read and Page Program need the same three address cycles fol-
lowing the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations
are selected by writing specific commands into the command register. Table 2. defines the specific commands of the SmartMedia.

Table 1.MEMORY ORGANIZATION

Memory Organization

Number of rows(Pages)

Number of columns

K9S6408V0X

66Mbit (69,206,016 bit)

16,384 rows

528 columns

K9S2808V0X

132Mbit (138,412,032 bit)

32,768 rows

528 columns

K9S5608V0X

264Mbit (276,824,064 bit)

65,536 rows

528 columns

Table 2. COMMAND SETS

NOTE: 1. The 00h command defines starting address of the 1st half of registers.The 01h command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, address pointer is automatically moved to the 1st half register(00h) on the
next cycle.

Caution : Any undefined command inputs are prohibited except for above command sets of Table2.

Function

1st. Cycle

2nd. Cycle

Acceptable Command during Busy

00h/01h

(1)

50h

Read ID

90h

Reset

FFh

Page Program

80h

10h

Block Erase

60h

D0h

Read Status

70h

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored and does not return the device to standby
mode.

Write Enable(WE)

The WE input controls writing to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.

Low Voltage Detect(LVD)

The LVD is used to detect the proper supply voltage electrically. By connecting this pin to Vss through a pull-down resister, it is pos-
sible to distinguish 3.3V product from 5V product. When 3.3V is applied as Vcc to pins 12 and 22, a 'High' level can be detected on
the system side if the device is a 3.3V product, and 'Low' level for 5V product.

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions otherwise noted.)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Operating

Current

Sequential Read

tRC=50ns, CE=V

, I

OUT

=0mA

Program

Erase

Stand-by Current(TTL)

CE=V

, WP=0V/V

Stand-by Current(CMOS)

CE=V

-0.2, WP=0V/V

Input Leakage Current

=0 to 3.6V

Output Leakage Current

OUT

=0 to 3.6V

Input High Voltage, All inputs

2.0

+0.3

Input Low Voltage, All inputs

-0.3

0.8

Output High Voltage Level

=-400

2.4

Output Low Voltage Level

=2.1mA

0.4

Output Low Current(R/B)

(R/B)

=0.4V

ABSOLUTE MAXIMUM RATINGS

NOTE :
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

+0.3V which, during transitions, may overshoot to V

+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to V

-0.6 to + 4.6

Temperature Under Bias

BIAS

-10 to +65

Storage Temperature

STG

-20 to +65

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, T

=0 to 55

Parameter

Symbol

Min

Typ.

Max

Unit

Supply Voltage

2.7

3.3

3.6

Supply Voltage

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

MODE SELECTION

NOTE : 1. X can be V

or V

IH.

2. WP should be biased to CMOS high or CMOS low for standby.

CLE

ALE

Mode

Read Mode Command Input

Address Input(3clock)

Write Mode Command Input

Address Input(3clock)

Data Input

sequential Read & Data Output

During Read(Busy)

During Program(Busy)

During Erase(Busy)

(1)

Write Protect

0V/V

(2)

Stand-by

CAPACITANCE

(

=25

C, V

=3.3V, f=1.0MHz)

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

I/O

=0V

Input Capacitance

=0V

VALID BLOCK

NOTE :
1. The

K9SXX08V0X

may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits

. Do not

erase or program factory-marked bad blocks.

Refer to the attached technical notes for an appropriate management of invalid blocks.

2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.
(Refer to the attached technical notes)

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

K9S6408V0X

1,014

1,020

1,024

Blocks

K9S2808V0X

1,004

1,024

K9S5608V0X

2013

2048

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

PROG

200

500

Number of Partial Program Cycles
in the Same Page

Main Array

Nop

cycles

Spare Array

cycles

Block Erase Time

BERS

AC TEST CONDITION

=0 to 55

C, V

=2.7V~3.6V unless otherwise noted)

Parameter

Value

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Times

5ns

Input and Output Timing Levels

1.5V

Output Load (3.0V +/-10%)

1 TTL GATE and CL=50pF

Output Load (3.3V +/-10%)

1 TTL GATE and CL=100pF

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

AC Characteristics for Operation

NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

Parameter

Symbol

Min

Max

Unit

Data Transfer from Cell to Register

CLE to RE Delay

CLR

ALE to RE Delay

Ready to RE Low

RE Pulse Width

WE High to Busy

100

Read Cycle Time

RE Access Time

REA

RE High to Output Hi-Z

RHZ

CE High to Output Hi-Z

CHZ

RE High Hold Time

REH

Output Hi-Z to RE Low

Last RE High to Busy (at sequential read)

100

CE High to Ready (in case of interception by CE at read)

CRY

50 +tr(R/B)

(1)

CE High Hold Time(at the last serial read)

(2)

CEH

100

WE High to RE Low

WHR

Device Resetting Time(Read/Program/Erase)

RST

5/10/500

(3)

AC Timing Characteristics for Command / Address / Data Input

NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

Parameter

Symbol

Min

Max

Unit

CLE setup Time

CLS

CLE Hold Time

CLH

CE setup Time

CE Hold Time

WE Pulse Width

(1)

ALE setup Time

ALS

ALE Hold Time

ALH

Data setup Time

Data Hold Time

Write Cycle Time

WE High Hold Time

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

SmartMedia Technical Notes

Identifying Invalid Block(s)

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. An invalid block(s) does not affect the performance
of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be
able to mask out the invalid block(s) via address mapping.

SSFDC Forum specifies the logical format and physical format to ensure compatibility of SmartMedia. Samsung pre-formats Smart-
Media in the Forum-compliant format prior to shipping. The physical format standard by SSFDC Forum specifies that invalid block
information is written at the 6th byte of spare area in invalid blocks with two or more "0" bits, while valid blocks are erased(FFh). Since
the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. There-
fore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid
block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original invalid block information is prohib-
ited.

Check "FFh" at the column address 517

Figure 3. Flow chart to create invalid block table.

Start

Set Block Address = 0

Check "FFh" ?

Increment Block Address

Last Block ?

End

Yes

Create (or update)

Invalid Block(s) Table

of the first page in the block

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

SmartMedia Technical Notes

(Continued)

Program Flow Chart

Start

I/O 6 = 1 ?

Write 00h

I/O 0 = 0 ?

If ECC is used, this verification

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

Write Address

Wait for tR Time

Verify Data

Program Completed

or R/B = 1 ?

Program Error

Yes

Program Error

Yes

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

operation is not needed.

Error in write or read operation

Over its life time, the additional invalid blocks may be developed during its use. Refer to the qualification report for the actual data.The
following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status failure during a page program does not affect the data
of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block
and reprogramming the current target data and copying the rest data of the replaced block. To improve the efficiency of memory
space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replace-
ment. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Write

Erase Failure

Status Read after Erase --> Block Replacement

Program Failure

Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Read

Single Bit Failure

Verify ECC -> ECC Correction

ECC

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Erase Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 60h

Write Block Address

Write D0h

Read Status Register

or R/B = 1 ?

Erase Error

Yes

: If erase operation results in an error, map out

the failing block and replace it with another block.

Erase Completed

Yes

Read Flow Chart

Start

Verify ECC

Write 00h

Write Address

Read Data

ECC Generation

Reclaim the Error

Page Read Completed

Yes

SmartMedia Technical Notes

(Continued)

Block Replacement

* Step1
When an error happens in the nth page of the Block 'A' during the program operation.
* Step2
Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B')
* Step3
Then, copy the data in the 1st ~ (n-1)th page of the Block 'A' to the same location of the Block 'B'.
* Step4
Do not erase or program to Block 'A' by creating an 'invalid Block' table or using other appropriate scheme.

Buffer memory of the controller.

1st

Block A

Block B

(n-1)th
nth

(page)

{

1st

(n-1)th
nth

(page)

{

an error occurs.

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h'
command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets
the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command, the
address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be inputted
before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting from
'B' area, '01h' command must be inputted right before '80h' command is written.

00h

(1) Command input sequence for programming 'A' area

Address / Data input

80h

10h

00h

80h

10h

Address / Data input

The address pointer is set to 'A' area(0~255), and sustained

01h

(2) Command input sequence for programming 'B' area

Address / Data input

80h

10h

01h

80h

10h

Address / Data input

'B', 'C' area can be programmed.
It depends on how many data are inputted.

'01h' command must be rewritten before
every program operation

The address pointer is set to 'B' area(256~512), and will be reset to
'A' area after every program operation is executed.

50h

(3) Command input sequence for programming 'C' area

Address / Data input

80h

10h

50h

80h

10h

Address / Data input

Only 'C' area can be programmed.

'50h' command can be omitted.

The address pointer is set to 'C' area(512~527), and sustained

'00h' command can be omitted.

It depends on how many data are inputted.

'A','B','C' area can be programmed.

Pointer Operation of the SmartMedia

Destination of the pointer

Command

Pointer position

Area

00h
01h
50h

0 ~ 255 byte

256 ~ 511 byte
512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

"A" area

256 Byte

(00h plane)

"B" area

(01h plane)

"C" area

(50h plane)

256 Byte

16 Byte

"A"

"B"

"C"

Internal

Page Register

Pointer select
commnad
(00h, 01h, 50h)

Pointer

Figure 4. Block Diagram of Pointer Operation

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

System Interface Using CE don't-care.

(Min. 10ns)

Start Add.(3Cycle)

80h

Data Input

CLE

ALE

I/O

Data Input

CE don't-care

10h

For an easier system interface, CE may be inactive during the data-loading or sequential read as shown below. The internal 528byte
page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would
provide significant savings in power consumption.

Start Add.(3Cycle)

00h

CLE

ALE

I/O

Data output (Sequential)

CE don't-care

R/B

CEA

out

REA

(Max. 45ns)

I/O

Figure 5. Program Operation with CE don't-care.

Figure 6. Read Operation with CE don't-care.

Must be held
low during tR.

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

READ1 OPERATION

(READ ONE PAGE)

CLE

R/B

I/O

ALE

Busy

00h or 01h A

~ A

Dout N

Dout N+1 Dout N+2

Dout N+3

Column
Address

Page(Row)
Address

RHZ

CHZ

Dout 527

CRY

Status Read Cycle

CLE

I/O

70h

Status Output

CLR

CLH

REA

RHZ

CHZ

WHR

CEA

CLS

CEH

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

READ1 OPERATION

(INTERCEPTED BY CE)

CLE

R/B

I/O

ALE

Busy

00h or 01h

~ A

Dout N

Dout N+1 Dout N+2

Dout N+3

Page(Row)
Address

Address

Column

CHZ

READ2 OPERATION

(READ ONE PAGE)

CLE

R/B

I/O

ALE

50H

~ A

Dout

Dout 527

M Address

511+M

Dout

511+M+1

: Valid Address

: Don

t care

Selected
Row

Start
address M

512

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

PAGE PROGRAM OPERATION

CLE

R/B

I/O

ALE

80h

70h

I/O

Din

10h

527

N+1

~ A

Sequential Data

Input Command

Column

Address

Page(Row)

Address

1 up to 528 Byte Data

Serial Input

Program

Command

Read Status

Command

I/O

=0 Successful Program

I/O

=1 Error in Program

PROG

SEQUENTIAL ROW READ OPERATION

(Within a block especially for 64Mb-Cdie and 128Mb Bdie)

CLE

R/B

I/O

ALE

00h

~ A

Busy

Output

~ A

Dout

N+1

Dout

N+2

Dout

527

Dout

527

Busy

M+1

Output

Ready

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

MANUFACTURE & DEVICE ID READ OPERATION

CLE

I/O 0 ~ 7

ALE

90h

Read ID Command

Maker Code

Device Code

00h

ECh

75h

Address. 1cycle

NOTE :
The 3rd byte of device IDs represents whether there is Unigue ID or not. If A5h is read out, that means that the Smart Media has the Unigue ID.

UniqueID Code

1st

2nd

3rd

REA

CLR

ID Definition Table
90 ID : Access command = 90H

READ ID (1)

Value

Description

Byte

ECh
*75h
A5h

Maker Code
Device Code
Unique1D code

K9S6408V0X : E6h

K9S2808V0X : 73h

K9S5608V0X : 75h

NOTE :
*Device Code : K9S6408V0X : E6h , K9S2808V0X : 73h , K9S5608V0X: 75h

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, sequential read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 10

s(t

). The system controller can detect the completion of this data transfer(tR) by monitoringing

the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by pulsing RE
sequentially. High to low transitions of the RE clock output the data starting from the selected column address up to the last column
address.
After the data of the last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10

s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way

the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command. Addresses A

to A

set the starting address of the spare area while

addresses A

to A

are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row

read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is
needed to move the pointer back to the main area. Figures 7 through 10 show typical sequence and timings for each read operation.

Figure 7. Read1 Operation

Start Add.(3Cycle)

00h

~ A

& A

~ A

Data Output (Serial Access)

(00h Command)

Data Field

Spare Field

CLE

ALE

R/B

I/O

* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.

(01h Command)*

Data Field

Spare Field

1st half array

2st half array

1st half array

2st half array

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Figure 8. Read2 Operation

50h

~ A

& A

~ A

Data Output(Serial Access)

Spare Field

CLE

ALE

R/B

Data Field

Spare Field

Start Add.(3Cycle)

~ A

Don

t Care)

I/O

Figure 9. Sequential Row Read1 Operation

00h

01h

~ A

& A

~ A

I/O

R/B

Start Add.(3Cycle)

Data Output

1st

2nd

Nth

(528 Byte)

The Sequential Read 1 and Read 2 operations are allowed only within a block and after the last page of a block
is readout, the sequential read operation must be terminated by bringing CE high. When the page address
moves onto the next block, read command and address must be given.

(00h Command)

1st half array 2nd half array

Data Field

Spare Field

1st
2nd

(01h Command)

Data Field

Spare Field

Nth

1st half array 2nd half array

1st
2nd
Nth

Block

1st half array 2nd half array

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Figure 10. Sequential Row Read2 Operation

PAGE PROGRAM

The device is programmed basically on a page basis, however it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation has the limit by its density. (See the Table of Program/Erase Characteristics) It is advis-
able not to program more often than recommend. It might cause failures due to disturbance when it exceeds its limits. The failure
mode could be that data "1" of the erased cell might be changed into data"0"of the programmed cell.
The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which
up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell. Serial data loading can be started from the 2nd half array by moving pointer. About the pointer
operation, please refer to the attached technical notes.The serial data loading period begins by inputting the Serial Data Input com-
mand(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do
not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previ-
ously entering the serial data will not initiate the programming process. The internal write-controller automatically executes the algo-
rithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process
starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller
can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the
Read Status command and Reset command are valid while programming is in progress. When the Page Program is completed, the
Write Status Bit(I/O 0) may be checked(Figure 11). The internal write verify detects only errors for "1"s that are not successfully pro-
grammed to "0"s. The command register remains in Read Status command mode until another valid command is written to the com-
mand register.

50h

~ A

& A

~ A

I/O

R/B

Start Add.(3Cycle)

Data Output

2nd

Nth

(16Byte)

1st

Figure 11. Program & Read Status Operation

80h

~ A

& A

~ A

I/O

R/B

Address & Data Input

I/O

Pass

528 Byte Data

10h

70h

Fail

PROG

~ A

Don

t Care)

Data Field

Spare Field

1st
Block
Nth

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

Figure 12. Block Erase Operation

BLOCK ERASE

The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A

to (A

: K9S6408V0X, A

: K9S2808V0X, A

: K9S5608V0X

)

is valid while A

to A

ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise
conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

60h

Block Add. : A

~ A

I/O

R/B

Address Input(2Cycle)

I/O

Pass

D0h

70h

Fail

BERS

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to Table3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
mode, a read command(00h or 50h) should be given before the sequential read cycle.

Read Status Register Definition

I/O #

Status

Definition

I/O 0

Program / Erase

"0" : Successful Program / Erase

"1" : Error in Program / Erase

I/O 1

Reserved for Future

Use

"0"

I/O 2

"0"

I/O 3

"0"

I/O 4

"0"

I/O 5

"0"

I/O 6

Device Operation

"0" : Busy "1" : Ready

I/O 7

Write Protect

"0" : Protected "1" : Not Protected

: K9S6408V0X

: K9S2808V0X

: K9S5608V0X

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Three read cycles sequentially output the manufacture code(ECH), the device code (

K9S6408V0X : E6h , K9S2808V0X : 73h ,

K9S5608V0X: 75h

), the UniqueID code(A5h) respectively. The command register remains in Read ID mode until further commands are

issued to it. Figure 13 shows the operation sequence.

CLE

I/O

ALE

90h

00h

Address. 1cycle

CEA

REA

ECh

Maker code

75h

Device code

A5h

UniqueID code

CLR

WHR

K9S6408V0X : E6h

K9S2808V0X : 73h

K9S5608V0X : 75h

Figure 14. RESET Operation

Table 4. Device Status

After Power-up

After Reset

Operation Mode

Waiting for next command

FFh

I/O

R/B

RST

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 14 below.

Figure 13. Read ID Operation

K9S2808V0C/B

SmartMedia

K9S5608V0C/B

K9S6408V0C/B

R/B
open drain output

Device

GND

where I

is the sum of the input currents of all devices tied to the R/B pin.

t
r
,
t
f

[
s
]

I
b

s
y

[
A

]

Rp(ohm)

Figure 15. Rp vs tr ,tf & Rp vs ibusy

Ibusy

Rp value guidance

Rp(max) is determined by maximum permissible limit of tr

ibusy

Rp(min) =

(Max.) - V

(Max.)

3.2V

8mA

Busy

Ready Vcc

@ Vcc = 3.3V, Ta = 25

C , C

= 100pF

2.0V

100n

200n

300n

189

290

381

4.2

3.3

1.65

1.1

0.825

0.8V

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read operations. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Figure 15). Its value can be
determined by the following guidance.

SmartMedia Dimensions

SmartMedia

DIMENSIONS

Unit:mm

0.15

0.05

22 PAD SOLID STATE FLOPPY DISK CARD (3.3V)

7
.
5

2
.
1

(
M

a
x
)

SOLID STATE PRODUCT OUTLINE

Contact Area

0.76

0.08

(+0.1mm package body surface)

1.5

0.1

27.0

0.5mm Chamfer
(3.3V Card)

4.2(Min)

5.0

33.0

0.2

45.0

0.1

4
.
5

(
M

i
n
)

37.0

0.1

5.0

0.2

Index Label Area

10.0

0.2

Write Protect Area

c
c

/
B

I
/
O

c
c

L
E

I
/
O

1
2
.
7

0
0

6.500

7.900

8.650

1
0
.
1

6
0

7
.
6

2
0

5
.
0

8
0

2
.
5

4
0

0
.
0

0
0

1
2

.
7
0

6.500

7.900

8.650

1
0

.
1
6

7
.
6
2
0

5
.
0
8
0

2
.
5
4
0

0
.
0
0
0

2.140 TYP

0.400 TYP

0.000

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K9Sxx08V0x

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