FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Document Title

256M x 8 Bit / 128M x 16 Bit / 512M x 8 Bit NAND Flash Memory

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.

Revision No

0.0

0.1

0.2

0.3

0.4

Remark

Advance

Preliminary

History

1. Initial issue

1. Add the Rp vs tr ,tf & Rp vs Ibusy graph for 1.8V device (Page 34)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 35)

The min. Vcc value 1.8V devices is changed.
K9F2GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V

Few current value is changed.
Before Unit : us

After

1. The 3rd Byte ID after 90h ID read command is don't cared.
The 5th Byte ID after 90h ID read command is deleted.
2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
3. Pb-free Package is added.
K9F2G08Q0M-PCB0,PIB0
K9F2G08U0M-PCB0,PIB0
K9F2G16U0M-PCB0,PIB0
K9F2G16Q0M-PCB0,PIB0

K9F2GXXQ0M

K9F2GXXU0M

Typ.

Max.

Typ.

Max.

100

±20

K9F2GXXQ0M

K9F2GXXU0M

Typ.

Max.

Typ.

Max.

±10

Draft Date

Sep. 19.2001

Nov. 22. 2002

Mar. 6.2003

Apr. 2. 2003

Apr. 9. 2003

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Document Title

256M x 8 Bit / 128M x 16 Bit/ 512M x 8 Bit NAND Flash Memory

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

Revision No

0.5

0.6

0.7

Remark

Preliminary

History

1. The value of AC parameters for K9F2G08U0M are changed.

2. The definition and value of setup and hold time are changed.

3. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 22~25)

tADL is the time from the WE rising edge of final address cycle

to the WE rising edge of first data cycle at program operation.

4. Added addressing method for program operation

1. PKG(TSOP1, WSOP1) Dimension Change

1. Technical note is changed
2. Notes of the AC timing characteristics are added
3. The description of Copy-back program is changed
4. 52ULGA Package is added

ITEM

K9F2G08U0M

Before

After

REH

REA

CEA

ADL

100

ITEM

K9F2G16U0M

K9F2GXXQ0M

K9F2G08U0M

CLS

CLH

ALS

ALH

Draft Date

Apr. 22.2004

May. 19. 2004

Jan. 21. 2005

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

GENERAL DESCRIPTION

FEATURES

· Voltage Supply
-2.7 V ~3.6 V
· Organization
- Memory Cell Array
-X8 device(K9F2G08X0M) : (256M + 8,192K)bit x 8bit
-X16 device(K9F2G16X0M) : (128M + 4,096K)bit x 16bit
- Data Register
-X8 device(K9F2G08X0M): (2K + 64)bit x8bit
-X16 device(K9F2G16X0M): (1K + 32)bit x16bit
- Cache Register
-X8 device(K9F2G08X0M) : (2K + 64)bit x8bit
-X16 device(K9F2G16X0M) : (1K + 32)bit x16bit
· Automatic Program and Erase
- Page Program
-X8 device(K9F2G08X0M) : (2K + 64)Byte
-X16 device(K9F2G16X0M) : (1K + 32)Word
- Block Erase
-X8 device(K9F2G08X0M) : (128K + 4K)Byte
-X16 device(K9F2G16X0M) : (64K + 2K)Word
· Page Read Operation
- Page Size
- X8 device(K9F2G08X0M) : 2K-Byte
- X16 device(K9F2G16X0M) : 1K-Word
- Random Read : 25

µs(Max.)

- Serial Access : 30ns(Min.)

256M x 8 Bit / 128M x 16 Bit/ 512M x 8 Bit NAND Flash Memory

· Fast Write Cycle Time
- Page Program time : 200

µs(Typ.)

- Block Erase Time : 2ms(Typ.)
· Command/Address/Data Multiplexed I/O Port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
· Command Register Operation
· Cache Program Operation for High Performance Program
· Power-On Auto-Read Operation
· Intelligent Copy-Back Operation
· Unique ID for Copyright Protection
· Package :
- K9F2GXXU0M-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F2GXXU0M-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9K4G08U1M-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 0.65 mm pitch)

Offered in 256Mx8bit or 128Mx16bit, the K9F2GXXU0M is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-
effective solution for the solid state mass storage market. A program operation can be performed in typical 200

µs on the 2112-

byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device)
or 64K-word(X16 device) block. Data in the data page can be read out at 30ns cycle time per byte(X8 device) or word(X16 device)..
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates
all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9F2GXXU0M

s extended reliability of 100K program/erase cycles by providing

ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2GXXU0M is an optimum solution for large nonvolatile
storage applications such as solid state file storage and other portable applications requiring non-volatility.

PRODUCT LIST

Part Number

Vcc Range

Organization

PKG Type

K9F2G08U0M-Y,P

2.7 ~ 3.6V

TSOP1

K9F2G16U0M-Y,P

X16

K9K4G08U1M-I

52ULGA

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

PIN CONFIGURATION (TSOP1)

K9F2GXXU0M-YCB0,PCB0/YIB0,PIB0

X16

48-pin TSOP1

Standard Type
12mm x 20mm

N.C

R/B

N.C

Vcc

Vss

N.C

CLE

ALE

N.C

I/O7

I/O6

I/O5

I/O4

N.C

PRE

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

R/B

N.C

Vcc

Vss

N.C

CLE

ALE

N.C

Vss

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

N.C

PRE

Vcc

N.C

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

Vss

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220AF

Unit :mm/Inch

0.787

±0.008

20.00

±0.20

#24

0.1

+0.

0
7

-0

.
0
3

+0.

003

-
0

.001

0197

#48

#25

488

.40

MAX

.00

472

0.1

004

MAX

0.2

010

()

0.039

±0.002

1.00

±0.05

0.002

0.05

MIN

0.047

1.20

MAX

0.45~0.75

0.018~0.030

0.724

±0.004

18.40

±0.10

0~8

010

0.2

TYP

125

.
0
75

0.0

3
5

.
0

0
3

-0

0
1

0.50

0.020

(

)

+0.

0
7

-0

.
0
3

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

1.00

2.00

7 6 5 4 3 2 1

1.0

12.00

±0.10

#A1

17.

±
0.

.00

0.1

12.00

±0.10

(Datum B)

(Datum A)

12.

10.00

0.5

12-

1.00±0.05

41-

0.70

0.05

Side View

(
Max

0.10 C

17.00

±0.10

Top View

Bottom View

D E

H J

PIN CONFIGURATION (ULGA)

K9K4G08U1M - ICB0/IIB0

52-ULGA (measured in millimeters)

Vcc

Vss

/RE1

/RE2

/CE1

/CE2

CLE1

CLE2

ALE1

ALE2

/WE1

/WE2

/WP1

/WP2

/RB1

/RB2

Vss

IO0-1

IO0-2

IO1-1

IO1-2

IO2-1

IO3-1

IO2-2

IO3-2

IO4-1

IO4-2

IO5-1

IO5-2

IO6-1

IO6-2

IO7-1

IO7-2

0.1

PACKAGE DIMENSIONS

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

PIN DESCRIPTION

NOTE : Connect all V

and V

pins of each device to common power supply outputs.

Do not leave V

or V

disconnected.

Pin Name

Pin Function

I/O

~ I/O

(K9F2G08X0M)

I/O

~ I/O

(K9F2G16X0M)

DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.

CLE

COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE

ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.

CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to 'Page read' section of Device operation .

READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.

WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.

R/B

READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.

PRE

POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.

Vcc

POWER
V

is the power supply for device.

Vss

GROUND

N.C

NO CONNECTION
Lead is not internally connected.

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

2K Bytes

64 Bytes

Figure 1-1. K9F2G08X0M (X8) Functional Block Diagram

Figure 2-1. K9F2G08X0M (X8) Array Organization

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

X-Buffers

Command

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

- A

Command

CE
RE
WE

CLE

I/0 0

I/0 7

128K Pages
(=2,048 Blocks)

2K Bytes

8 bit

64 Bytes

1 Block = 64 Pages
(128K + 4k) Byte

I/O 0 ~ I/O 7

1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2048 Blocks
= 2112 Mbits

Row Address

Page Register

ALE PRE

2048M + 64M Bit

NAND Flash

ARRAY

(2048 + 64)Byte x 131072

Y-Gating

Cache Register

Row Address

Column Address

Data Register & S/A

Row Address

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

1K Words

32 Words

Figure 1-2. K9F2G16X0M (X16) Functional Block Diagram

Figure 2-2. K9F2G16X0M (X16) Array Organization

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O8 ~ 15

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

X-Buffers

Command

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

- A

Command

CE
RE
WE

CLE

I/0 0

I/0 15

128K Pages
(=2,048 Blocks)

1K Words

16 bit

32 Words

1 Block = 64 Pages
(64K + 2k) Word

I/O 0 ~ I/O 15

1 Page = (1K + 32)Words
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K) Words
1 Device = (1K+32)Word x 64Pages x 2048 Blocks
= 2112 Mbits

Row Address

Page Register

ALE PRE

2048M + 64M Bit

NAND Flash

ARRAY

(1024 + 32)Word x 131072

Y-Gating

Cache Register

Row Address

Column Address

Data Register & S/A

Row Address

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Product Introduction

The K9F2GXXU0M is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8(X8 device) or
1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or
1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056-
word(X16 device) cache register are serially connected to each other. Those serially connected registers are connected to memory
cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program opera-
tions. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in
a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells
reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 2048 separately erasable 128K-byte(X8 device) or 64K-word(X16 device) blocks. It indicates
that the bit by bit erase operation is prohibited on the K9F2GXXU0M.

The K9F2GXXU0M has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). This scheme dramatically reduces pin
counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-
mands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other
commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execu-
tion. The 256M byte(X8 device) or 128M word(X16 device) physical space requires 29(X8) or 28(X16) addresses, thereby requiring
five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the
same five address cycles following the required command input. In Block Erase operation, however, only the three row address
cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific
commands of the K9F2GXXU0M.

The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performance may be dramatically improved by cache
program when there are lots of pages of data to be programmed.

The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address
input after power-on.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

NOTE : 1. Random Data Input/Output can be executed in a page.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Function

1st. Cycle

2nd. Cycle

Acceptable Command during Busy

Read 00h

30h

Read for Copy Back

00h

35h

Read ID

90h

Reset

FFh

Page Program

80h

10h

Cache Program

80h

15h

Copy-Back Program

85h

10h

Block Erase

60h

D0h

Random Data Input

85h

Random Data Output

05h

E0h

Read Status

70h

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions otherwise noted.)

NOTE : V

can undershoot to -0.4V and V

can overshoot to V

+0.4V for durations of 20 ns or less.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Operating

Current

Page Read with Serial
Access

tRC=30ns, CE=V

OUT

=0mA

Program

Erase

Stand-by Current(TTL)

CE=V

, WP=PRE=0V/V

Stand-by Current(CMOS)

CE=V

-0.2,

WP=PRE=0V/V

µA

Input Leakage Current

=0 to Vcc(max)

±10

Output Leakage Current

OUT

=0 to Vcc(max)

±10

Input High Voltage

IH*

0.8xVcc

Vcc+0.3

Input Low Voltage, All inputs

IL*

-0.3

0.2xVcc

Output High Voltage Level

K9F2GXXU0M :I

=-400

µA

2.4

Output Low Voltage Level

K9F2GXXU0M :I

=2.1mA

0.4

Output Low Current(R/B)

(R/B)

K9F2GXXU0M :V

=0.4V

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F2GXXU0M-XCB0

=0 to 70

°C, K9F2GXXU0M-XIB0

=-40 to 85

°C)

Parameter

Symbol

Min

Typ.

Max

Unit

Supply Voltage

2.7

3.3

3.6

Supply Voltage

ABSOLUTE MAXIMUM RATINGS

NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

CC,

+0.3V which, during transitions, may overshoot to V

+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to V

IN/OUT

-0.6 to + 4.6

Temperature Under Bias

K9F2GXXU0M-XCB0

BIAS

-10 to +125

°C

K9F2GXXU0M-XIB0

-40 to +125

Storage Temperature

K9F2GXXU0M-XCB0

STG

-65 to +150

°C

K9F2GXXU0M-XIB0

Short Circuit Current

Ios

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

CAPACITANCE

(

=25

°C, V

=3.3V, f=1.0MHz)

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

I/O

=0V

Input Capacitance

=0V

VALID BLOCK

NOTE :
1. The

device

may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-

sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits

. Do not erase or pro-

gram factory-marked bad blocks.

Refer to the attached technical notes for appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase

cycles.

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

2,008

2,048

Blocks

AC TEST CONDITION

(K9F2GXXU0M-XCB0 :TA=0 to 70

°C, K9F2GXXU0M-XIB0:TA=-40 to 85°C

K9F2GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)

Parameter

K9F2GXXU0M

Input Pulse Levels

0V to Vcc

Input Rise and Fall Times

5ns

Input and Output Timing Levels

Vcc/2

Output Load

1 TTL GATE and CL=50pF

Program / Erase Characteristics

NOTE : 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25

2. Max. time of

CBSY

depends on timing between internal program completion and data in

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

PROG

200

700

µs

Dummy Busy Time for Cache Program

CBSY

700

µs

Number of Partial Program Cycles
in the Same Page

Main Array

Nop

cycles

Spare Array

cycles

Block Erase Time

BERS

MODE SELECTION

NOTE : 1. X can be V

or V

IH.

2. WP and PRE should be biased to CMOS high or CMOS low for standby.

CLE

ALE

PRE

Mode

Read Mode

Command Input

Address Input(5clock)

Write Mode

Command Input

Address Input(5clock)

Data Input

Data Output

During Read(Busy)

During Program(Busy)

During Erase(Busy)

Write Protect

0V/V

Stand-by

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

AC Characteristics for Operation

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

2. For cache program operation, the whole AC Charcateristics must be same as that of K9F2G16U0M.

Parameter

Symbol

Min

Max

Unit

K9F2G16U0M

K9F2G08U0M

K9F2G16U0M

K9F2G08U0M

Data Transfer from Cell to Register

µs

ALE to RE Delay

CLE to RE Delay

CLR

Ready to RE Low

RE Pulse Width

WE High to Busy

100

Read Cycle Time

RE Access Time

REA

CE Access Time

CEA

RE High to Output Hi-Z

RHZ

CE High to Output Hi-Z

CHZ

RE or CE High to Output hold

RE High Hold Time

REH

Output Hi-Z to RE Low

RE High to WE Low

RHW

100

WE High to RE Low

WHR

Device Resetting Time
(Read/Program/Erase)

RST

5/10/500

µs

AC Timing Characteristics for Command / Address / Data Input

NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. For cache program operation, the whole AC Charcateristics must be same as that of K9F2G16U0M.

Parameter

Symbol

Min

Max

Unit

K9F2G16U0M

K9F2G08U0M

K9F2G16U0M

K9F2G08U0M

CLE setup Time

CLS

CLE Hold Time

CLH

CE setup Time

CE Hold Time

WE Pulse Width

ALE setup Time

ALS

ALE Hold Time

ALH

Data setup Time

Data Hold Time

Write Cycle Time

WE High Hold Time

ALE to Data Loading Time

ADL

100

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

NAND Flash Technical Notes

Identifying Initial Invalid Block(s)

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The
information regarding the initial invalid block(s) is so called as the invalid block information. Devices with initial invalid block(s) have
the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does
not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor.
The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h
block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

All device locations are erased(FFh for X8, FFFFh for X16) except locations where the initial invalid block(s) information is written
prior to shipping. The invalid block(s) status is defined by the 1st byte(X8 device) or 1st word(X16 device) in the spare area. Sam-
sung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh(X8) or non-FFFFh(X16) data at the column
address of 2048(X8 device) or 1024(X16 device). Since the initial invalid block information is also erasable in most cases, it is
impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid
block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.

Check "FFh( or FFFFh)" at the column address

Figure 3. Flow chart to create initial invalid block table.

Start

Set Block Address = 0

Check "FFh

Increment Block Address

Last Block ?

End

Yes

Create (or update)

Initial Invalid Block(s) Table

of the 1st and 2nd page in the block

2048(X8 device) or 1024(X16 device)

or FFFFh" ?

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

NAND Flash Technical Notes

(Continued)

Program Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

Program Completed

or R/B = 1 ?

Program Error

Yes

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block
failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail during a page program does not
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an
erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC
must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should
be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those
reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Write

Erase Failure

Status Read after Erase --> Block Replacement

Program Failure

Status Read after Program --> Block Replacement

Read

Single Bit Failure

Verify ECC -> ECC Correction

ECC

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Erase Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 60h

Write Block Address

Write D0h

Read Status Register

or R/B = 1 ?

Erase Error

Yes

: If erase operation results in an error, map out

the failing block and replace it with another block.

Erase Completed

Yes

Read Flow Chart

Start

Verify ECC

Write 00h

Write Address

Read Data

ECC Generation

Reclaim the Error

Page Read Completed

Yes

NAND Flash Technical Notes

(Continued)

Write 30h

Block Replacement

* Step1
When an error happens in the nth page of the Block 'A' during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B')
* Step3
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'.
* Step4
Do not erase or program to Block 'A' by creating an 'invalid Block' table or other appropriate scheme.

Buffer memory of the controller.

1st

Block A

Block B

(n-1)th
nth

(page)

{

1st

(n-1)th
nth

(page)

{

an error occurs.

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

System Interface Using CE don't-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal
2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system
design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activat-
ing CE during the data-loading and serial access would provide significant savings in power consumption.

Figure 4. Program Operation with CE don't-care.

Address(5Cycles)

80h

Data Input

CLE

ALE

Data Input

CE don't-care

10h

Address(5Cycle)

00h

CLE

ALE

Data Output(serial access)

CE don't-care

R/B

CEA

out

REA

I/O

Figure 5. Read Operation with CE don't-care.

30h

I/Ox

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

K9F2G16X0M : I/O

15 must be set to "0"

K9F2G16X0M : I/O

15 must be set to "0"

Command Latch Cycle

CLE

ALE

Command

Address Latch Cycle

CLS

CLH

ALS

ALH

NOTE

Device

I/O

DATA

ADDRESS

I/Ox

Data In/Out

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

K9F2G08X0M(X8)

I/O 0 ~ I/O 7

~2112byte

A0~A7

A8~A11

A12~A19

A20~A27

A28

K9F2G16X0M(X16)

I/O 0 ~ I/O 15

~1056word

A0~A7

A8~A10

A11~A18

A19~A26

A27

I/Ox

CLE

ALE

Col. Add1

ALS

ALH

ALS

ALH

ALS

ALH

ALS

I/Ox

Col. Add2

Row Add1

Row Add2

ALH

ALS

Row Add3

ALH

CLS

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

ge Program Operation with Rand

om Dat

a
In

put

CLE

R/B

ALE

I/O

10h

ri
al

a
ta

I
npu

t Command

Col

u
mn A

ddr

ess

Addr

ess

Seri

Inp

u
t

ogr

a
n
d

ad Stat

a
n
d

Random Dat

Inp

u
t Command

n
Ad

dres

Din

Ser

i
al

I
nput

I
/Ox

Col

.
A

dd1

Col

.
A

dd2

Row Add1

Row Add2

Col

.
A

dd1

Col

.
A

dd2

Row A

d
d
3

ADL

NOTES

L

is t

h
e

i
m

h
e

r
i
sing edg

o
f
fi

nal add

ress

cycl

t
o

e WE

rising edg

o
f
f
i
rst dat

a cycle

ADL

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

py-Back Program

Operatio

n W

i
th Random

t
a
Input

CLE

R/B

ALE

I/
O

85h

Colu

n
A

d
dr

ess

ad S

t
at

a
n
d

I/O

=
0
Succe

ssf

I/O

r
i
n

Pro

g
r
a
m

PROG

Busy

py-

k Da

t Co

a
n
d

lum

n
A

d
dr

w Ad

dres

a
ta

I/O

l
A

d
d
1

l
A

d
d
2

w A

d
d
1

w A

d
d
2

l
A

d
d
1

l
A

d
d
2

w A

d
d
1

w A

d
d
2

w A

d
d
3

w A

d
d
3

ADL

NOTES

L

is t

h
e

i
m

h
e

r
i
sing edg

o
f
fi

nal add

ress

cycl

t
o

e WE

rising edg

o
f
f
i
rst dat

a cycle

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Cach

e Pro

m Operation

i
l
a
b
l
e
on

l
y

w

i
t
h
i
n a bl

o
ck)

CLE

R/B

ALE

n N

e
r
i
al Data

I
n
put Co

and

o
l
u
mn A

d
dr

Ser

i
al I

n
put

P
r
ogra

Max.

63 ti

mes re

peat

abl

C
o
mma

L
a
st

put

ogr

CBSY

x. 7

0
0
u
s

u
m

y
)

n N

10h

tCPROG

I/
O

80h

Col

Add

,2 &

Row

d1,2

R/B

ddress &

Data

I
npu

s
s
&

n
p

15h

Addr

ess &

n
p

15h

Addr

ess &

10h

Ex.) Cach

e Pro

CBS

CBSY

PRO

P
r
ogr

am Con

f
i
r
m

C
o
mma

(Tr

ue)

o
w A

ddress

I
/Ox

I/O

C
o
l
Add1

Col

Add2

Row A

dd1

Row A

dd2

Col

Add1

Col

d
d2

w
A

d
d
1

Row A

d
d2

w A

d
d
3

w A

d
d
3

tADL

NOTES

L

is t

h
e

i
m

h
e

r
i
sing edg

o
f
fi

nal add

ress

cycl

t
o

e WE

rising edg

o
f
f
i
rst dat

a cycle

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Device Operation

PAGE READ

Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h-30h to the command
register along with five address cycles. In two consecutive read operations, the second one doesn't need 00h command, which five
address cycles and 30h command initiates that operation. Once the command is latched, it does not need to be written for the follow-
ing page read operation. Two types of operations are available : random read, serial page read .
The random read mode is enabled when the page address is changed. The 2112 bytes(X8 device) or 1056 words(X16 device) of
data within the selected page are transferred to the data registers in less than 25

µs(t

). The system controller can detect the comple-

tion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be
read out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output
the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

Address(5Cycle)

00h

Col Add1,2 & Row Add1,2,3

Data Output(Serial Access)

Data Field

Spare Field

CLE

ALE

R/B

30h

I/Ox

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Figure 7. Random Data Output In a Page

Address

00h

Data Output

R/B

30h

Address

05h

E0h

5Cycles

2Cycles

Data Output

Data Field

Spare Field

Data Field

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112(X8 device) or words up to 1056(X16 device), in a single page program cycle. The number of consecutive partial
page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(X8
device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte, X16 device:1time/8word).
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which
up to 2112bytes(X8 device) or 1056words(X16 device) of data may be loaded into the data register, followed by a non-volatile pro-
gramming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-
gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.

Figure 8. Program & Read Status Operation

80h

R/B

Address & Data Input

I/O

Pass

Data

10h

70h

Fail

PROG

I/Ox

Col Add1,2 & Row Add1,2,3

"0"

"1"

Col Add1,2 & Row Add1,2,3

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Cache Program

Figure 9. Random Data Input In a Page

80h

R/B

Address & Data Input

I/O

Pass

10h

70h

Fail

PROG

85h

Address & Data Input

Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis-
ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data
stored in data register are programmed into memory cell.

After writing the first set of data up to 2112byte(X8 device) or 1056word(X16 device) into the selected cache registers, Cache Pro-
gram command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY)
and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data
registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy sta-
tus bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data is
inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of
the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of
data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal program-
ming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be
progammed with actual Page Program command (10h).

Figure 10. Cache Program

(available only within a block)

80h

R/B

80h

Address &
Data Input

15h

80h

Address &
Data Input

15h

80h

Address &
Data Input

10h

CBSY

PROG

70h

Address &
Data Input*

15h

I/Ox

Col Add1,2 & Row Add1,2,3

Col Add1,2

Data

Col Add1,2 & Row Add1,2,3

Data

Col Add1,2 & Row Add1,2,3

Data

"0"

"1"

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Copy-Back Program

Figure 11. Page Copy-Back program Operation

00h

R/B

Add.(5Cycles)

I/O

Pass

85h

70h

Fail

PROG

Add.(5Cycles)

Source Address

Destination Address

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2112byte(X8 device) or 1056word(X16 device) data into the internal data buffer. As soon as the device returns to Ready
state, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program Con-
firm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple dis-
tant portions of the source page is allowed as shown in Figure 11. "When there is a program-failure at Copy-Back operation,
error is reported by pass/fail status. But if the soure page has an error bit by charge loss, accumulated copy-back
operations could also accumulate bit errors. In this case, verifying the source page for a bit error is recommended before
Copy-back program"

35h

NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple-
tion of the previous cycle, which can be expressed as the following formula.

tPROG= Program time for the last page+ Program time for the ( last -1 )th page
- (Program command cycle time + Last page data loading time)

10h

Figure 12. Page Copy-Back program Operation with Random Data Input

00h

R/B

Add.(5Cycles)

85h

70h

PROG

Add.(5Cycles)

Source Address

Destination Address

Data

35h

10h

85h

Data

Add.(2Cycles)

There is no limitation for the number of repetition.

I/Ox

Col. Add1,2 & Row Add1,2,3

Col Add1,2

NOTE: It's prohibited to operate Copy-Back program from an odd address page(source page) to an even address page(target page) or from an even
address page(source page) to an odd address page(target page). Therefore, the Copy-Back program is permitted just between odd address pages or
even address pages

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Figure 13. Block Erase Operation

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A

to A

(X8) or A

to A

(X16) is valid while A

to A

(X8) or A

to A

(X16) is ignored. The Erase

Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.

60h

Block Add. : A

~ A

(X8)

R/B

Address Input(3Cycle)

I/O

Pass

D0h

70h

Fail

BERS

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.

Table2. Read Staus Register Definition

NOTE :

1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.

2. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.

I/O No.

Page Program

Block Erase

Cache Prorgam

Read

Definition

I/O 0

Pass/Fail

Pass/Fail(N)

Not use

Pass : "0" Fail : "1"

I/O 1

Not use

Pass/Fail(N-1)

Not use

Pass : "0" Fail : "1"

I/O 2

Not use

Don't -cared

I/O 3

Not Use

Don't -cared

I/O 4

Not Use

Don't -cared

I/O 5

Ready/Busy

True Ready/Busy

Ready/Busy

Busy : "0" Ready : "1"

I/O 6

Ready/Busy

Busy : "0" Ready : "1"

I/O 7

Write Protect

Protected : "0" Not Protected

I/O 8~15

(X16 device

only)

Not use

Don't -care

I/Ox

or A

~ A

(X16)

"0"

"1"

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

Figure 14. Read ID Operation

CLE

I/O

ALE

90h

00h

Address. 1cycle

Maker code

Device code

CEA

REA

Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 50h respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.

Device

80h

4th Cyc.*

ECh

Figure 15. RESET Operation

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.

FFh

I/O

R/B

RST

WHR

CLR

Code*

Device

Device Code*(2nd Cycle)

3rd Cycle

4th Cycle*

K9F2G08U0M

DAh

80h

15h

K9F2G16U0M

CAh

80h

55h

Table3. Device Status

After Power-up

After Reset

PRE status

High

Low

Waiting for next command

Operation Mode

First page data access is ready

00h command is latched

FLASH MEMORY

Preliminary

K9F2G08U0M K9F2G16U0M

K9K4G08U1M

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be
determined by the following guidance.

R/B

open drain output

Device

GND

t
r
,
t
f [s

]

Ibusy [A]

Rp(ohm)

Figure 17. Rp vs tr ,tf & Rp vs ibusy

Ibusy

ibusy

Busy

Ready Vcc

@ Vcc = 3.3V, Ta = 25

°C , C

= 50pF

VOH

50n

100n

150n

100

150

200

1.8

2.4

1.2

0.8

0.6

VOL

where I

is the sum of the input currents of all devices tied to the R/B pin.

Rp value guidance

Rp(max) is determined by maximum permissible limit of tr

Rp(min, 3.3V part) =

(Max.) - V

(Max.)

3.2V

8mA

3.3V device - V

: 0.4V, V

: 2.4V

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