Introduction

1.1 About this document

This document lists detailed information about the SJA2020 device. It focuses on factual
information like pin information, register views, characteristics etc. Short descriptions are
used to outline the concept of the features and functions. More details and background on
developing applications for this device is given in the SJA2020 User manual (see

Ref. 1

No explicit references are made to the User manual.

Please refer to the SJA2020 Application note `Known issues' (see

Ref. 2

) for corrections

and additional product information.

1.2 Intended audience

This document is written for engineers evaluating and/or developing systems, hard- and/or
software for the SJA2020. Some basic knowledge of ARM processors and architecture
and ARM7 in particular is assumed (see

Ref. 3

General description

2.1 Architectural overview

The SJA2020 consists of an ARM7TDMI-S processor with real-time emulation support,
the AMBA Advanced High-performance Bus (AHB) for interface to the on-chip memory
controllers, a DTL bus (a universal Philips interface) for interface to the interrupt controller
and three VLSI Peripheral Buses (VPB - a compatible superset of ARMs AMBA advanced
peripheral bus) for connection to the on-chip peripherals clustered in so-called
subsystems. The SJA2020 configures the ARM7TDMI-S processor in little endian byte
order. All peripherals run on the same system clock frequency as the ARM7TDMI-S
processor to minimize the access latency time. The AHB2VPB bridge used in the
subsystems contain a write-ahead buffer of 1 deep. This implies that when the ARM7
writes to a register located at the VPB side of the bridge, it will continue even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.

2.2 ARM7TDMI-S processor

The ARM7TDMI-S is a general purpose 32-bit processor, which offers high performance
and very low power consumption. The ARM architecture is based on Reduced Instruction
Set Computer (RISC) principles, and the instruction set and related decode mechanism
are much simpler than those of microprogrammed Complex Instruction Set Computers
(CISC). This simplicity results in a high instruction throughput and impressive real-time
interrupt response from a small and cost-effective controller core.

SJA2020

ARM7 microcontroller with CAN and LIN controllers

Rev. 01 -- 5 April 2006

Objective data sheet

SJA2020_1

Objective data sheet

Rev. 01 -- 5 April 2006

2 of 176

Philips Semiconductors

SJA2020

ARM7 microcontroller with CAN and LIN controllers

Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:

�

Standard 32-bit ARM set

�

16-bit Thumb set

The Thumb set's 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM's performance advantage over a
traditional 16-bit controller using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM controller connected to a 16-bit memory system.

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S data sheet (see

Ref. 3

2.3 On-chip flash memory system

The SJA2020 includes up to 384 kB flash memory system. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed in-system via a serial port, like e.g. CAN. The
application program may also erase and/or program the flash while the application is
running, allowing a great degree of flexibility for data storage field upgrades.

2.4 On-chip static RAM

The SJA2020 includes a 24 kB static RAM memory that may be used for code and/or data
storage.

Features

3.1 General

ARM7TDMI-S processor at 60 MHz maximum

Up to 384 kB on-chip flash program memory

24 kB static RAM

One 550 UART with 16 bytes TX and RX FIFO depths

Three full-duplex SPIs with 16 bits wide, 8 locations deep TX FIFO and RX FIFO

Four 32-bit timers containing each four capture and compare registers linked to I/Os

10-bit, 400 ksample/s, 4-channel ADC with external trigger start option

Real time clock with on-chip 32 kHz crystal oscillator and (battery) supply

32-bit watchdog with timer change protection

SJA2020_1

Objective data sheet

Rev. 01 -- 5 April 2006

3 of 176

Philips Semiconductors

SJA2020

ARM7 microcontroller with CAN and LIN controllers

94 general purpose I/O pins with programmable pull-up

Vectored interrupt controller with 16 priority levels

External 8-bit, 16-bit or 32-bit bus with four memory banks

Standard ARM test and debug interface with real-time in-circuit emulator

Dual power supply:

CPU operating voltage: 1.8 V

�

5 %

I/O operating voltage: 3.3 V

5 V tolerant port pins (without pull-up)

Configurable system power management

Twelve level sensitive external interrupt pins

Processor wake-up from power down via external interrupt pins, CAN or LIN activity

On-chip low power ring-oscillator with operating range from 25 kHz to 1 MHz

On-chip crystal oscillator with operating range from 10 MHz to 20 MHz

On-chip PLL allows CPU operation up to maximum CPU rate of 60 MHz

Automotive product qualification according AEC-Q100 Rev-F:

Temperature grade 2 compliant; ambient operating temperature from

�

C to +105

�

Boundary scan test supported

Small 144-pin LQFP package

3.2 Flash memory

Consisting of sectors of 8 kB

Supporting in-system and in-application programming

Fast programming capability at 4 Mbit/s

Provisions against over-burning and over-erasing

Source code protection

3.3 CAN gateway

Six CAN controllers

Full CAN mode for message reception

Triple transmit buffers with automatic priority scheduling

Extensive global CAN acceptance filter for high performance gateway functionality

3.4 LIN master controller

Four dedicated LIN master controllers

Four standard 450 UARTs with LIN enhancement for LIN slaves or general purposes

Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

SJA2020HL/623

[1]

LQFP144 plastic low profile quad flat package; 144 leads;

body 20

�

1.4 mm

SOT486-1

SJA2020_1

Objective data sheet

Rev. 01 -- 5 April 2006

4 of 176

Philips Semiconductors

SJA2020

ARM7 microcontroller with CAN and LIN controllers

[1]

SJA2020HL/623 has 384 kB flash consisting of 48 sectors of 8 kB.

Block diagram

Fig 1.

Block diagram

001aaa165

AHB2VPB BRIDGE

PERIPHERAL SUBSYSTEM

ARM7TDMI-S

SJA2020

AHB WRAPPER

1149.1 JTAG TEST and

DEBUG INTERFACE

FLASH CONTROLLER

384 kB FLASH

STATIC RAM CONTROLLER

24 kB FLASH

AHB2DTL ADAPTER

VECTORED INTERRUPT

CONTROLLER

CAPTURE and COMPARE

TIMER 0, 1, 2, 3

GENERAL PURPOSE

I/O 0, 1, 2

550 UART

AHB2VPB BRIDGE

IVN SUBSYSTEM

2 kB STATIC RAM

GLOBAL ACCEPTANCE

FILTER

CAN CONTROLLER

0, 1, 2, 3, 4, 5

450 UART 0, 1, 2, 3

LIN MASTER

CONTROLLER 0, 1, 2, 3

JTAGSEL

TRST_N

TMS

TCK

TDI

RTCK

TDO

CAP0[0] to CAP3[3]

MAT0[0] to MAT3[3]

P0[0:31]

P2[0:29]

P1[0:31]

TXDC0 to TXDC5

RXDC0 to RXDC5

TXDL0 to TXDL3

RXDL0 to RXDL3

TXD

RXD

AHB DECODER

EXTERNAL MEMORY

CONTROLLER

AHB2VPB BRIDGE

GENERAL SUBSYSTEM

SPI 0, 1, 2

10-BIT ADC

ADC INTERFACE

SYSTEM CONTROL UNIT

WATCHDOG TIMER

EVENT ROUTER

REAL TIME CLOCK

32 kHz OSCILLATOR

POWER-ON RESET

CLOCK GENERATION UNIT

10 MHz to 20 MHz OSCILLATOR

LOW POWER PLL

LOW POWER RING OSCILLATOR

POWER-ON RESET

CORE SUPPLY 1.8 V

I/O PINS SUPPLY 3.3 V

XOUT_OSC

XIN_OSC

RESET_N

XOUT_RTC

AI0 to AI3

XIN_RTC

CS0 to CS3

WE_N

OE_N

BLS0 to BLS3

D[0:31]

A[0:23]

SCS0 to SCS2

SCK0 to SCK2

SDI0 to SCI2

SDO0 to SDO2

DD(ADC)

VREFN

EI0 to EI3

RXDC0 to RXDC5

RXDL0 to RXDL3

DD(RTC)

SS(RTC)

DD(OSC_PLL)

SS(OSC)

SS(PLL)

DD(CORE)

SS(CORE)

DD(IO)

SS(IO)

SJA2020_1

Objective data sheet

Rev. 01 -- 5 April 2006

5 of 176

Philips Semiconductors

SJA2020

ARM7 microcontroller with CAN and LIN controllers

Pinning information

6.1 Pinning

6.2 Pin description

Fig 2.

Pin configuration for SOT486-1

SJA2020HL

108

001aac517

Table 2:

LQFP144 pin assignment

Symbol

Pin

Description

Default function

Function 1

Function 2

Function 3

JTAGSEL

TAP controller select input; LOW level selects ARM debug mode and HIGH
level selects boundary scan and flash programming; pulled-up internally

RESET_N

external reset input; pulled-up internally (active LOW)

SS(RTC)

real time clock oscillator ground

XOUT_RTC

real time clock crystal output

XIN_RTC

real time clock crystal input or external clock input

DD(RTC)

real time clock oscillator supply voltage

SS(OSC)

oscillator ground

XOUT_OSC

oscillator crystal output

XIN_OSC

oscillator crystal input or external clock input

DD(OSC_PLL)

oscillator and PLL supply voltage

SS(PLL)

PLL ground

P0[31]/SDO0

GPIO 0; pin 31

SPI0 SDO

P0[30]/SDI0

GPIO 0; pin 30

SPI0 SDI

P0[29]/SCK0

GPIO 0; pin 29

SPI0 SCK

P0[28]/SCS0

GPIO 0; pin 28

SPI0 SCS

SS(IO)

I/O pins ground

P0[27]/SDO1

GPIO 0; pin 27

SPI1 SDO

DD(CORE)

core supply voltage 1.8 V

SS(CORE)

digital core ground

P0[26]/SDI1

GPIO 0; pin 26

SPI1 SDI

P0[25]/SCK1

GPIO 0; pin 25

SPI1 SCK

Электронный компонент: SJA2020

Document Outline