2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

CONTENTS

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

Data manager

7.2

Encoder

7.3

Output interface/DACs

7.4

Synchronization

7.5

C-bus interface

7.6

Input levels and formats

7.7

Bit allocation map

7.8

C-bus format

7.9

Slave receiver

7.10

Slave transmitter

CHARACTERISTICS

8.1

Explanation of RTCI data bits

8.2

Teletext timing

APPLICATION INFORMATION

9.1

Analog output voltages

PACKAGE OUTLINE

SOLDERING

11.1

Introduction to soldering surface mount
packages

11.2

Reflow soldering

11.3

Wave soldering

11.4

Manual soldering

11.5

Suitability of surface mount IC packages for
wave and reflow soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I

C COMPONENTS

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

FEATURES

Monolithic CMOS 3.3 V device

Digital PAL/NTSC encoder

System pixel frequency 13.5 MHz

Accepts MPEG decoded data on 8-bit wide input port;
input data format C

-Y-C

(CCIR 656)

Three Digital-to-Analog Converters (DACs) for Y, C
and CVBS two times oversampled with 10-bit resolution

Real-time control of subcarrier

Cross-colour reduction filter

Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter

Line 23 Wide Screen Signalling (WSS) encoding

Fast I

C-bus control port (400 kHz)

Encoder can be master or slave

Programmable horizontal and vertical input
synchronization phase

Programmable horizontal sync output phase

Internal Colour Bar Generator (CBG)

2 bytes in lines 20 (NTSC) for copy guard

management system can be loaded via I

C-bus

Down mode of DACs

Controlled rise/fall times of synchronization and
blanking output signals

Macrovision

(1)

Pay-per-View copy protection system

rev. 7.01 and rev. 6.1 as option; this applies to
SAA7120H only. The device is protected by USA patent
numbers 4631603, 4577216 and 4819098 and other
intellectual property rights. Use of the Macrovision
anti-copy process in the device is licensed for
non-commercial home use only. Reverse engineering or
disassembly is prohibited. Please contact your nearest
Philips Semiconductors sales office for more information

QFP44 package.

GENERAL DESCRIPTION

The SAA7120H; SAA7121H encodes digital YUV video
data to an NTSC or PAL CVBS or S-video signal.

The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip DACs.

(1) Macrovision

is a trademark of the Macrovision Corporation.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7120H

QFP44

plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10

1.75 mm

SOT307-2

SAA7121H

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

QUICK REFERENCE DATA

BLOCK DIAGRAM

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

DDA

analog supply voltage

3.1

3.3

3.5

DDD

digital supply voltage

3.0

3.3

3.6

DDA

analog supply current

DDD

digital supply current

input signal voltage levels

TTL compatible

o(p-p)

analog output signal voltages Y, C and CVBS without load
(peak-to-peak value)

1.35

load resistance

300

lf(i)

low frequency integral linearity error

LSB

lf(d)

low frequency differential linearity error

LSB

amb

ambient temperature

Fig.1 Block diagram.

handbook, full pagewidth

C-BUS

INTERFACE

DATA

MANAGER

ENCODER

SYNC

CLOCK

OUTPUT

INTERFACE

43 37

34 35

25, 28,
31

MP7

MP0

TTX

5, 18, 38

6, 17, 39

1, 20, 22,
23, 26, 29

32, 33

RESET SDA SCL

RCV1

RCV2

TTXRQ

XCLK

XTALO

XTALI

LLC

VDDA4

VSSA1
VSSA2

CVBS

C-bus

control

C-bus

control

C-bus

control

C-bus

control

C-bus

control

VSSD1,
VSSD2,

VSSD3

VDDD1,
VDDD2,

VDDD3

VDDA1,
VDDA2,

VDDA3

RES

RTCI

clock

and timing

CB-CR

9 to 16

MBH787

SAA7120H
SAA7121H

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

PINNING

SYMBOL

PIN

TYPE

DESCRIPTION

RES

reserved

test pin; connected to digital ground for normal operation

LLC

line-locked clock; this is the 27 MHz master clock for the encoder

SSD1

supply

digital ground 1

DDD1

supply

digital supply voltage 1

RCV1

I/O

raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal

RCV2

I/O

raster control 2 for video port; this pin provides an HS pulse of programmable
length or receives an HS pulse

MP7

MPEG ports; inputs for

"CCIR 656" style multiplexed C

-Y-C

data

MP6

MP5

MP4

MP3

MP2

MP1

MP0

DDD2

supply

digital supply voltage 2

SSD2

supply

digital ground 2

RTCI

real-time control input; if the LLC clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to the RTCO pin of the respective decoder to improve
the signal quality

RES

reserved

the I

C-bus slave address select input pin; LOW: slave address = 88H,

HIGH = 8CH

RES

reserved

RES

reserved

analog output of the chrominance signal

DDA1

supply

analog supply voltage 1 for the C DAC

RES

reserved

analog output of VBS signal

DDA2

supply

analog supply voltage 2 for the Y DAC

RES

reserved

CVBS

analog output of the CVBS signal

DDA3

supply

analog supply voltage 3 for the CVBS DAC

SSA1

supply

analog ground 1 for the DACs

SSA2

supply

analog ground 2 for the oscillator and reference voltage

XTALO

crystal oscillator output

XTALI

crystal oscillator input; if the oscillator is not used, this pin should be connected to
ground

DDA4

supply

analog supply voltage 4 for the oscillator and reference voltage

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

XCLK

clock output of the crystal oscillator

SSD3

supply

digital ground 3

DDD3

supply

digital supply voltage 3

RESET

Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I

C-bus receiver waits for the START condition.

SCL

C-bus serial clock input

SDA

I/O

C-bus serial data input/output

TTXRQ

teletext request output, indicating when bit stream is valid

TTX

teletext bit stream input

SYMBOL

PIN

TYPE

DESCRIPTION

handbook, full pagewidth

SAA7120H
SAA7121H

MBH790

RES

LLC

VDDD1

VSSD1

RCV1

RCV2

MP7

MP6

MP5

MP4

MP3

MP2

MP1

MP0

DDD2

SSD2

RTCI

RES

33 VSSA2

VSSA1

VDDA3

VDDA2

VDDA1

CVBS

RES

TTX

TTXRQ

SDA

SCL

XCLK

XTALI

XTALO

DDD3

DDA4

SSD3

RESET

Fig.2 Pin configuration.

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

FUNCTIONAL DESCRIPTION

The digital video encoder encodes digital luminance and
colour difference signals into analog CVBS and
simultaneously S-video signals. NTSC-M, PAL-B/G and
sub-standards are supported. Both interlaced and
non-interlaced operation is possible for all standards.

The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of

"RS-170-A" and "CCIR 624".

For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.

The total filter transfer characteristics are illustrated in
Figs 3 to 6. The DACs for Y, C and CVBS are realized with
full 10-bit resolution.

The 8-bit multiplexed C

-Y-C

formats are

"CCIR 656"

(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode.

It is also possible to connect a Philips digital video decoder
(SAA7111 or SAA7151B) to this encoder. By connecting
pin RTCI to pin RTCO of a decoder, information about the
actual subcarrier, PAL-ID and (with SAA7111 and newer
types) definite subcarrier phase can be inserted.

The digital video encoder synthesizes all necessary
internal signals, colour subcarrier frequency and
synchronization signals from that clock.

Wide screen signalling data can be loaded via the I

C-bus

and is inserted into line 23 for standards using 50 Hz field
rate.

The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with Macrovision.

A number of possibilities are provided for setting different
video parameters, such as:

Black and blanking level control

Colour subcarrier frequency

Variable burst amplitude, etc.

During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the I

C-bus interface to abort any running bus transfer and

sets register 3A to 03H, register 61 to 06H, registers 6BH
and 6EH to 00H and bit TTX60 to 0. No other control
registers are influenced by a reset.

7.1

Data manager

Real-time arbitration on the data stream to be encoded is
performed in the data manager.

A pre-defined colour look-up table located in this block can
be read out in a pre-defined sequence (8 steps per active
video line), achieving a colour bar test pattern generator
without the need for an external data source. The colour
bar function is under software control only.

7.2

Encoder

7.2.1

IDEO PATH

The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.

Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). A blanking level can be set after insertion of
a fixed synchronization pulse tip level in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process such as additional insertion of AGC super-white
pulses (programmable in height) are supported by the
SAA7120H only.

In order to enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, providing luminance in 10-bit resolution. This filter is
also used to define smoothed transients for
synchronization pulses and blanking period. The transfer
characteristics of the luminance interpolation filter are
illustrated in Figs 5 and 6.

Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs 3 and 4.

The amplitude, beginning and ending of the inserted burst,
is programmable in a certain range that is suitable for
standard signals and for special effects. Behind the
succeeding quadrature modulator, colour in a 10-bit
resolution is provided on the subcarrier.

The numeric ratio between Y and C outputs is in
accordance with the respective standards.

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

7.2.2

ELETEXT INSERTION AND ENCODING

Pin TTX receives a WST or NABTS teletext bitstream
sampled at the LLC clock. At each rising edge of output
signal (TTXRQ) a single teletext bit has to be provided
after a programmable delay at the input pin.

Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.

TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines which are selectable independently for
both fields. The internal insertion window for text is set to
360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.10.

7.2.3

LOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification
of closed caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.

The actual line number where data is to be encoded in, can
be modified in a certain range.

The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.

Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.

7.2.4

NTI

TAPING

(SAA7120H

ONLY

)

For more information contact your nearest Philips
Semiconductors sales office.

7.3

Output interface/DACs

In the output interface, encoded Y and C signals are
converted from digital-to-analog in a 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.

The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitude at the input of
the DAC for CVBS is reduced by

with respect to

Y and C DACs to make maximum use of conversion
ranges.

Outputs of the DACs can be set together in two groups, via
software control, to a minimum output voltage for either
purpose.

7.4

Synchronization

The synchronization of the SAA7120H; SAA7121H is able
to operate in two modes; slave mode and master mode.

In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and the on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it also can be used to set the horizontal phase.

If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be applied to pin RCV2. Timing
and trigger behaviour can also be influenced for the signal
at pin RCV2.

If there are missing pulses at RCV1 and/or RCV2, the time
base of the IC runs free, thus an arbitrary number of
synchronization slopes may miss, but no additional pulses
(with the incorrect phase) must occur.

If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.

Alternatively, the device can be triggered by auxiliary
codes in a

"CCIR 656" data stream at the MP port.

In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the device can
output:

A Vertical Sync (VS) signal with 3 or 2.5 lines duration

An odd/even signal which is LOW in odd fields

A Field Sequence (FSEQ) signal which is HIGH in the
first of 4 or 8 fields respectively.

On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.

The polarity of both RCV1 and RCV2 is selectable by
software control.

The length of a field and the start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

7.5

C-bus interface

The I

C-bus interface is a standard slave transceiver,

supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.

The I

C-bus slave address is defined as 88H with pin 21

(SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.

7.6

Input levels and formats

The SAA7120H; SAA7121H expects digital Y, C

and C

data with levels (digital codes) in accordance

with

"CCIR 601".

For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.

Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.

Table 1

"CCIR 601" signal component levels

COLOUR

SIGNALS

White

235

128

Yellow

210

146

Cyan

170

166

Green

145

Magenta

106

202

222

Red

240

Blue

240

110

Black

128

Table 2

8-bit multiplexed format (similar to

"CCIR 601")

TIME

BITS

Sample

Luminance pixel number

Colour pixel number

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2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

7.7

Bit allocation map

Table 3

Slave receiver (slave address 88H or 8CH)

REGISTER FUNCTION

SUBADDR

DATA BYTE

(1)

Null

00H to 25H

Wide screen signal

26H

WSS7

WSS6

WSS5

WSS4

WSS3

WSS2

WSS1

WSS0

Wide screen signal

27H

WSSON

WSS13

WSS12

WSS11

WSS10

WSS9

WSS8

Real-time control, burst start

28H

DECCOL

DECFIS

BS5

BS4

BS3

BS2

BS1

BS0

Burst end

29H

BE5

BE4

BE3

BE2

BE1

BE0

Copy guard odd 0

2AH

CGO07

CGO06

CGO05

CGO04

CGO03

CGO02

CGO01

CGO00

Copy guard odd 1

2BH

CGO17

CGO16

CGO15

CGO14

CGO13

CGO12

CGO11

CGO10

Copy guard even 0

2CH

CGE07

CGE06

CGE05

CGE04

CGE03

CGE02

CGE01

CGE00

Copy guard even 1

2DH

CGE17

CGE16

CGE15

CGE14

CGE13

CGE12

CGE11

CGE10

Copy guard enable

2EH

CGEN1

CGEN0

Null

2FH to 39H

Input port control

3AH

CBENB

SYMP

Y2C

UV2C

Chrominance phase

5AH

CHPS7

CHPS6

CHPS5

CHPS4

CHPS3

CHPS2

CHPS1

CHPS0

Gain U

5BH

GAINU7

GAINU6

GAINU5

GAINU4

GAINU3

GAINU2

GAINU1

GAINU0

Gain V

5CH

GAINV7

GAINV6

GAINV5

GAINV4

GAINV3

GAINV2

GAINV1

GAINV0

Gain U MSB, real-time control,
black level

5DH

GAINU8

DECOE

BLCKL5

BLCKL4

BLCKL3

BLCKL2

BLCKL1

BLCKL0

Gain V MSB, real-time control,
blanking level

5EH

GAINV8

DECPH

BLNNL5

BLNNL4

BLNNL3

BLNNL2

BLNNL1

BLNNL0

CCR, blanking level VBI

5FH

CCRS1

CCRS0

BLNVB5

BLNVB4

BLNVB3

BLNVB2

BLNVB1

BLNVB0

Null

60H

Standard control

61H

DOWN

INPI

YGS

SCBW

PAL

FISE

RTC enable, burst amplitude

62H

RTCE

BSTA6

BSTA5

BSTA4

BSTA3

BSTA2

BSTA1

BSTA0

Subcarrier 0

63H

FSC07

FSC06

FSC05

FSC04

FSC03

FSC02

FSC01

FSC00

Subcarrier 1

64H

FSC15

FSC14

FSC13

FSC12

FSC11

FSC10

FSC09

FSC08

Subcarrier 2

65H

FSC23

FSC22

FSC21

FSC20

FSC19

FSC18

FSC17

FSC16

Subcarrier 3

66H

FSC31

FSC30

FSC29

FSC28

FSC27

FSC26

FSC25

FSC24

Line 21 odd 0

67H

L21O07

L21O06

L21O05

L21O04

L21O03

L21O02

L21O01

L21O00

Line 21 odd 1

68H

L21O17

L21O16

L21O15

L21O14

L21O13

L21O12

L21O11

L21O10

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2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Note

1. All bits labelled `0' are reserved. They must be programmed with logic 0.

Line 21 even 0

69H

L21E07

L21E06

L21E05

L21E04

L21E03

L21E02

L21E01

L21E00

Line 21 even 1

6AH

L21E17

L21E16

L21E15

L21E14

L21E13

L21E12

L21E11

L21E10

RCV port control

6BH

SRCV11

SRCV10

TRCV2

ORCV1

PRCV1

CBLF

ORCV2

PRCV2

Trigger control

6CH

HTRIG7

HTRIG6

HTRIG5

HTRIG4

HTRIG3

HTRIG2

HTRIG1

HTRIG0

Trigger control

6DH

HTRIG10

HTRIG9

HTRIG8

VTRIG4

VTRIG3

VTRIG2

VTRIG1

VTRIG0

Multi control

6EH

SBLBN

PHRES1

PHRES0

FLC1

FLC0

Closed caption, teletext enable

6FH

CCEN1

CCEN0

TTXEN

SCCLN4

SCCLN3

SCCLN2

SCCLN1

SCCLN0

RCV2 output start

70H

RCV2S7

RCV2S6

RCV2S5

RCV2S4

RCV2S3

RCV2S2

RCV2S1

RCV2S0

RCV2 output end

71H

RCV2E7

RCV2E6

RCV2E5

RCV2E4

RCV2E3

RCV2E2

RCV2E1

RCV2E0

MSBs RCV2 output

72H

RCV2E10

RCV2E9

RCV2E8

RCV2S10

RCV2S9

RCV2S8

TTX request H start

73H

TTXHS7

TTXHS6

TTXHS5

TTXHS4

TTXHS3

TTXHS2

TTXHS1

TTXHS0

TTX request H delay

74H

TTXHD7

TTXHD6

TTXHD5

TTXHD4

TTXHD3

TTXHD2

TTXHD1

TTXHD0

Vsync shift

75H

VS_S2

VS_S1

VS_S0

TTX odd request vertical start

76H

TTXOVS7

TTXOVS6

TTXOVS5

TTXOVS4

TTXOVS3

TTXOVS2

TTXOVS1

TTXOVS0

TTX odd request vertical end

77H

TTXOVE7

TTXOVE6

TTXOVE5

TTXOVE4

TTXOVE3

TTXOVE2

TTXOVE1

TTXOVE0

TTX even request vertical start

78H

TTXEVS7

TTXEVS6

TTXEVS5

TTXEVS4

TTXEVS3

TTXEVS2

TTXEVS1

TTXEVS0

TTX even request vertical end

79H

TTXEVE7

TTXEVE6

TTXEVE5

TTXEVE4

TTXEVE3

TTXEVE2

TTXEVE1

TTXEVE0

First active line

7AH

FAL7

FAL6

FAL5

FAL4

FAL3

FAL2

FAL1

FAL0

Last active line

7BH

LAL7

LAL6

LAL5

LAL4

LAL3

LAL2

LAL1

LAL0

MSB vertical

7CH

TTX60

LAL8

FAL8

TTXEVE8

TTXOVE8

TTXEVS8

TTXOVS8

Null

7DH

Disable TTX line

7EH

LINE12

LINE11

LINE10

LINE9

LINE8

LINE7

LINE6

LINE5

Disable TTX line

7FH

LINE20

LINE19

LINE18

LINE17

LINE16

LINE15

LINE14

LINE13

REGISTER FUNCTION

SUBADDR

DATA BYTE

(1)

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

7.8

C-bus format

Table 4

C-bus address; see Table 5

Table 5

Explanation of Table 4

Notes

1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read; no subaddressing with read.

2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.

7.9

Slave receiver

Table 6

Subaddresses 26H and 27H

Table 7

Subaddresses 28H and 29H

SLAVE ADDRESS

ACK SUBADDRESS

ACK DATA 0

ACK --------

DATA n

ACK P

PART

DESCRIPTION

START condition

SLAVE ADDRESS

1000 100X or 1000 110X; note 1

ACK

acknowledge, generated by the slave

SUBADDRESS; note 2

subaddress byte

DATA

data byte

--------

continued data bytes and ACKs

STOP condition

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

WSS

wide screen signalling bits

3 to 0 = aspect ratio

7 to 4 = enhanced services

10 to 8 = subtitles

13 to 11 = reserved

WSSON

wide screen signalling output is disabled; default after reset

wide screen signalling output is enabled

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

REMARKS

starting point of burst in clock cycles

PAL: BS = 33 (21H); default after reset

NTSC: BS = 25 (19H)

ending point of burst in clock cycles

PAL: BE = 29 (1DH); default after reset

NTSC: BE = 29 (1DH)

DECCOL

disable colour detection bit of RTCI input

enable colour detection bit of RTCI input

bit RTCE must be set to logic 1 (see Fig.9)

DECFIS

field sequence as FISE in subaddress 61

field sequence as FISE bit in RTCI input

bit RTCE must be set to logic 1 (see Fig.9)

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 8

Subaddresses 2AH to 2DH

Table 9

Subaddress 2EH

Table 10 Subaddress 3AH

Table 11 Subaddress 5AH

DATA BYTE

DESCRIPTION

REMARKS

CGO0

first byte of copy guard data, odd field

LSBs of the respective bytes are encoded
immediately after run-in and framing code,
the MSBs of the respective bytes have to
carry the parity bit, in accordance with the
definition of line 20 encoding format

CGO1

second byte of copy guard data, odd field

CGE0

first byte of copy guard data, even field

CGE1

second byte of copy guard data, even field

DATA BYTE

DESCRIPTION

CCEN1

CCEN0

copy guard encoding off

enables encoding in field 1 (odd)

enables encoding in field 2 (even)

enables encoding in both fields

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

UV2C

, C

data are twos complement

, C

data are straight binary; default after reset

Y2C

Y data is twos complement

Y data is straight binary; default after reset

SYMP

horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after
reset

horizontal and vertical trigger is decoded out of

"CCIR 656" compatible data at MP port

CBENB

data from input ports is encoded; default after reset

colour bar with fixed colours is encoded

DATA BYTE

DESCRIPTION

VALUE

RESULT

CHPS

phase of encoded colour subcarrier
(including burst) relative to horizontal
sync; can be adjusted in steps of
360/256 degrees

00H

PAL-B/G and data from input ports

2AH

PAL-B/G and data from look-up table

88H

NTSC-M and data from input ports

AAH

NTSC-M and data from look-up table

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 12 Subaddresses 5BH and 5DH

Table 13 Subaddresses 5CH and 5EH

Table 14 Subaddress 5DH

Notes

1. Output black level/IRE = BLCKL

2/6.29 + 34.0.

2. Output black level/IRE = BLCKL

2/6.18 + 31.7.

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

GAINU

variable gain for
C

signal; input

representation in
accordance with
"CCIR 601"

white-to-black = 92.5 IRE

GAINU =

2.17

nominal to +2.16

nominal

GAINU = 0

output subcarrier of U contribution = 0

GAINU = 118 (76H)

output subcarrier of U contribution = nominal

white-to-black = 100 IRE

GAINU =

2.05

nominal to +2.04

nominal

GAINU = 0

output subcarrier of U contribution = 0

GAINU = 125 (7DH)

output subcarrier of U contribution = nominal

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

GAINV

variable gain for
C

signal; input

representation in
accordance with
"CCIR 601"

white-to-black = 92.5 IRE

GAINV =

1.55

nominal to +1.55

nominal

GAINV = 0

output subcarrier of V contribution = 0

GAINV = 165 (A5H)

output subcarrier of V contribution = nominal

white-to-black = 100 IRE

GAINV =

1.46

nominal to +1.46

nominal

GAINV = 0

output subcarrier of V contribution = 0

GAINV = 175 (AFH)

output subcarrier of V contribution = nominal

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BLCKL

variable black level; input
representation in
accordance with
"CCIR 601"

white-to-sync = 140 IRE;
note 1

recommended value: BLCKL = 42 (2AH)

BLCKL = 0; note 1

output black level = 34 IRE

BLCKL = 63 (3FH); note 1

output black level = 54 IRE

white-to-sync = 143 IRE;
note 2

recommended value: BLCKL = 35 (23H)

BLCKL = 0; note 2

output black level = 32 IRE

BLCKL = 63 (3FH); note 2

output black level = 52 IRE

DECOE

real-time control

logic 0

disable odd/even field control bit from RTCI

logic 1

enable odd/even field control bit from RTCI
(see Fig.9)

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 15 Subaddress 5EH

Notes

1. Output black level/IRE = BLNNL

2/6.29 + 25.4.

2. Output black level/IRE = BLNNL

2/6.18 + 25.9; default after reset: 35H.

Table 16 Subaddress 5FH

Table 17 Logic levels and function of CCRS

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BLNNL

variable blanking level

white-to-sync = 140 IRE;
note 1

recommended value: BLNNL = 46 (2EH)

BLNNL = 0; note 1

output blanking level = 25 IRE

BLNNL = 63 (3FH); note 1

output blanking level = 45 IRE

white-to-sync = 143 IRE;
note 2

recommended value: BLNNL = 53 (35H)

BLNNL = 0; note 2

output blanking level = 26 IRE

BLNNL = 63 (3FH); note 2

output blanking level = 46 IRE

DECPH

real-time control

logic 0

disable subcarrier phase reset bit from RTCI

logic 1

enable subcarrier phase reset bit from RTCI
(see Fig.9)

DATA BYTE

DESCRIPTION

BLNVB

variable blanking level during vertical blanking interval is typically identical to value of BLNNL

CCRS

select cross-colour reduction filter in luminance; see Table 17

CCRS1

CCRS0

DESCRIPTION

no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5

cross-colour reduction #1 active; for overall transfer characteristic see Fig.5

cross-colour reduction #2 active; for overall transfer characteristic see Fig.5

cross-colour reduction #3 active; for overall transfer characteristic see Fig.5

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 18 Subaddress 61H

Table 19 Subaddress 62H

Table 20 Subaddress 62H

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

FISE

864 total pixel clocks per line; default after reset

858 total pixel clocks per line

PAL

NTSC encoding (non-alternating V component)

PAL encoding (alternating V component); default after reset

SCBW

enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4)

standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); default after reset

YGS

luminance gain for white

black 100 IRE; default after reset

luminance gain for white

black 92.5 IRE including 7.5 IRE set-up of black

INPI

PAL switch phase is nominal; default after reset

PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 19

DOWN

DACs for CVBS, Y and C in normal operational mode; default after reset

DACs for CVBS, Y and C forced to lowest output voltage

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

RTCE

no real-time control of generated subcarrier frequency; default after reset

real-time control of generated subcarrier frequency through SAA7151B or SAA7111;
for timing see Fig.9

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BSTA

amplitude of colour burst; input
representation in accordance
with

"CCIR 601"

white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding

recommended value:
BSTA = 63 (3FH)

BSTA = 0 to 2.02

nominal

white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding

recommended value:
BSTA = 45 (2DH)

BSTA = 0 to 2.82

nominal

white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding

recommended value:
BSTA = 67 (43H)

BSTA = 0 to 1.90

nominal

white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding

recommended value:
BSTA = 47 (2FH); default after
reset

BSTA = 0 to 3.02

nominal

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 21 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)

Note

1. Examples:

a) NTSC-M: f

= 227.5, f

llc

= 1716

FSC = 569408543 (21F07C1FH).

b) PAL-B/G: f

= 283.7516, f

llc

= 1728

FSC = 705268427 (2A098ACBH).

Table 22 Subaddresses 67H to 6AH

Table 23 Subaddress 6BH

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

FSC0 to
FSC3

= subcarrier frequency (in

multiples of line frequency);
f

llc

= clock frequency (in

multiples of line frequency)

note 1

FSC3 = most significant byte;
FSC0 = least significant byte

DATA BYTE

DESCRIPTION

REMARKS

L21O0

first byte of captioning data, odd field

LSBs of the respective bytes are encoded
immediately after run-in and framing code, the
MSBs of the respective bytes have to carry the
parity bit, in accordance with the definition of
line 21 encoding format

L21O1

second byte of captioning data, odd field

L21E0

first byte of extended data, even field

L21E1

second byte of extended data, even field

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

PRCV2

polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset

polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively

ORCV2

pin RCV2 is switched to input; default after reset

pin RCV2 is switched to output

CBLF

if ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is
defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset

if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset

if ORCV2 = HIGH, pin RCV2 provides a `composite-blanking-not' signal, for example a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval,
which is defined by FAL and LAL

if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal

PRCV1

polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset

polarity of RCV1 as output is active LOW, falling edge is taken when input

ORCV1

pin RCV1 is switched to input; default after reset

pin RCV1 is switched to output

TRCV2

horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of "

CCIR 656" input (at bit SYMP = HIGH); default after reset

horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)

SRCV1

defines signal type on pin RCV1; see Table 24

FSC

round

llc

------

;

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 24 Logic levels and function of SRCV1

Table 25 Subaddresses 6CH and 6DH

Table 26 Subaddress 6DH

Table 27 Subaddress 6EH

Table 28 Logic levels and function of PHRES

DATA BYTE

AS OUTPUT

AS INPUT

FUNCTION

SRCV11

SRCV10

vertical sync each field; default after reset

frame sync (odd/even)

FSEQ

field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)

not applicable

DATA BYTE

DESCRIPTION

HTRIG

sets the horizontal trigger phase related to signal on RCV1 or RCV2 input

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; reference mark: analog output horizontal sync
(leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H (398H)

DATA BYTE

DESCRIPTION

VTRIG

sets the vertical trigger phase related to signal on RCV1 input

increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH)

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

SBLBN

vertical blanking is defined by programming of FAL and LAL; default after reset

vertical blanking is forced in accordance with

"CCIR 624" (50 Hz) or RS170A (60 Hz)

PHRES

selects the phase reset mode of the colour subcarrier generator; see Table 28

FLC

field length control; see Table 29

DATA BYTE

DESCRIPTION

PHRES1

PHRES0

no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset

reset every two lines

reset every eight fields

reset every four fields

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 29 Logic levels and function of FLC

Table 30 Subaddress 6FH

Table 31 Logic levels and function of CCEN

Table 32 Subaddresses 70H to 72H

Table 33 Subaddresses 73H and 74H

DATA BYTE

DESCRIPTION

FLC1

FLC0

interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset

non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz

non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz

DATA BYTE

LOGIC
LEVEL

DESCRIPTION

CCEN

enables individual line 21 encoding; see Table 31

TTXEN

disables teletext insertion; default after reset

enables teletext insertion

SCCLN

selects the actual line, where closed caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems

DATA BYTE

DESCRIPTION

CCEN1

CCEN0

line 21 encoding off; default after reset

enables encoding in field 1 (odd)

enables encoding in field 2 (even)

enables encoding in both fields

DATA BYTE

DESCRIPTION

RCV2S

start of output signal on pin RCV2

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; first active pixel at analog outputs
(corresponding input pixel coinciding with RCV2) at RCV2S = 11AH (0FDH)

RCV2E

end of output signal on pin RCV2

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; last active pixel at analog outputs
(corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H)

DATA BYTE

DESCRIPTION

REMARKS

TTXHS

start of signal on pin TTXRQ; see Fig.10

PAL: TTXHS = 42H

NTSC: TTXHS = 54H

TTXHD

indicates the delay in clock cycles between rising edge of
TTXRQ output and valid data at pin TTX

minimum value: TTXHD = 2

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 34 Subaddress 75H

Table 35 Subaddresses 76H, 77H and 7CH

Table 36 Subaddresses 78H, 79H and 7CH

Table 37 Subaddresses 7AH to 7CH

Table 38 Subaddress 7CH

DATA BYTE

DESCRIPTION

REMARKS

VS_S

vertical sync shift between RCV1 and RCV2 (switched to
output); in master mode it is possible to shift Hsync (RCV2;
CBLF = 0) against Vsync (RCV1; SRCV1 = 00)

standard value: VS_S = 3

DATA BYTE

DESCRIPTION

REMARKS

TTXOVS

first line of occurrence of signal on pin TTXRQ in odd field

PAL: TTXOVS = 05H;
NTSC: TTXOVS = 06H

line = (TTXOVS + 4) for M-systems

line = (TTXOVS + 1) for other systems

TTXOVE

last line of occurrence of signal on pin TTXRQ in odd field

PAL: TTXOVE = 16H;
NTSC: TTXOVE = 10H

line = (TTXOVE + 3) for M-systems

line = TTXOVE for other systems

DATA BYTE

DESCRIPTION

REMARKS

TTXEVS

first line of occurrence of signal on pin TTXRQ in even field

PAL: TTXEVS = 04H;
NTSC: TTXEVS = 05H

line = (TTXEVS + 4) for M-systems

line = (TTXEVS + 1) for other systems

TTXEVE

last line of occurrence of signal on pin TTXRQ in even field

PAL: TTXEVE = 16H;
NTSC: TTXEVE = 10H

line = (TTXEVE + 3) for M-systems

line = TTXEVE for other systems

DATA BYTE

DESCRIPTION

FAL

first active line: measured in lines; FAL = 0 coincides with the first field synchronization pulse

first active line = (FAL + 4) for M systems

first active line = (FAL + 1) for other systems

LAL

last active line: measured in lines; LAL = 0 coincides with the first field synchronization pulse

last active line = (LAL + 3) for M-systems

last active line = LAL for other systems

DATA BYTE

LOGIC LEVEL

DESCRIPTION

TTX60

enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset

enables world standard teletext 60 Hz (FISE = 1)

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Table 39 Subaddresses 7EH and 7FH

In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up.

7.10

Slave transmitter

Table 40 Slave transmitter (slave address 89H or 8DH)

Table 41 No subaddress

DATA BYTE

DESCRIPTION

LINE

individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate); this bit mask is effective only, if the lines are enabled by
TTXOVS/TTXOVE and TTXEVS/TTXEVE

SUBADDRESS

DATA BYTE

Status byte

VER2

VER1

VER0

CCRDO

CCRDE

FSEQ2

FSEQ1

O_E

DATA BYTE

LOGIC LEVEL

DESCRIPTION

VER

version identification of the device: it will be changed with all versions of the IC that
have different programming models; current version is 001 binary

CCRDO

closed caption bytes of the odd field have been encoded

the bit is reset after information has been written to the subaddresses
67H and 68H; it is set immediately after the data has been encoded

CCRDE

closed caption bytes of the even field have been encoded

the bit is reset after information has been written to the subaddresses
69H and 6AH; it is set immediately after the data has been encoded

FSEQ

state of the internal field sequence counter, with bit O_E as LSB
(repetition rate: NTSC = 4 fields, PAL = 8 fields)

O_E

during even field

during odd field

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

CHARACTERISTICS

DDD

= 3.0 to 3.6 V; T

amb

= 0 to 70

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Supply

DDA

analog supply voltage

3.1

3.5

DDD

digital supply voltage

3.0

3.6

DDA

analog supply current

note 1

DDD

digital supply current

DDD

= 3.3 V; note 1

Inputs: LLC, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX

LOW-level input voltage

0.5

+0.8

HIGH-level input voltage

2.0

DDD

+ 0.3

input leakage current

input capacitance

clocks

data

I/Os at
high-impedance

Outputs: RCV1, RCV2 and TTXRQ

LOW-level output voltage

= 2 mA

0.4

HIGH-level output voltage

2 mA

2.4

C-bus: SDA and SCL

LOW-level input voltage

0.5

+0.3V

DDD

HIGH-level input voltage

0.7V

DDD

+ 0.3

input current

= LOW or HIGH

+10

LOW-level output voltage (pin SDA)

= 3 mA

0.4

output current

during acknowledge

Clock timing: LLC

LLC

cycle time

note 2

duty factor t

HIGH

LLC

note 3

rise time

note 2

fall time

note 2

Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX

SU;DAT

input data set-up time

HD;DAT

input data hold time

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

Notes

1. At maximum supply voltage with highly active input signals.

2. The data is for both input and output direction.

3. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.

4. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of

subcarrier frequency and line/field frequency.

5. For full digital range, without load, V

DDA

= 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output

voltage (digital zero at DAC) is 0.2 V.

Crystal oscillator

nominal frequency (usually 27 MHz)

3rd harmonic

MHz

f/f

permissible deviation of nominal frequency

note 4

+50

RYSTAL SPECIFICATION

amb

ambient temperature

load capacitance

series resistance

motional capacitance (typical)

1.5

20%

1.5 + 20%

parallel capacitance (typical)

3.5

20%

3.5 + 20%

Data and reference signal output timing

output load capacitance

7.5

output hold time

output delay time

C, Y and CVBS outputs

o(p-p)

output signal voltage (peak-to-peak value)

note 5

1.25

1.50

int

internal serial resistance

output load resistance

300

output signal bandwidth of DACs

3 dB

MHz

lf(i)

low frequency integral linearity error of DACs

LSB

lf(d)

low frequency differential linearity error of DACs

LSB

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

8.1

Explanation of RTCI data bits

1. The HPLL increment is not evaluated by the

SAA7120H; SAA7121H.

2. The SAA7120H; SAA7121H generates the subcarrier

frequency from the FSCPLL increment if enabled
(see item 7.).

3. The PAL bit indicates the line with inverted (R

component of colour difference signal.

4. If the reset bit is enabled (RTCE = 1; DECPH = 1;

PHRES = 00), the phase of the subcarrier is reset in
each line whenever the reset bit of RTCI input is set to
logic 1.

5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the

SAA7120H; SAA7121H takes this bit instead of the
FISE bit in subaddress 61H.

6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1),

the SAA7120H; SAA7121H ignores its internally
generated odd/even flag and takes the odd/even bit
from RTCI input.

7. If the colour detection bit is enabled (RTCE = 1;

DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the SAA7120H; SAA7121H. In the other
case (colour detection bit = 1) the subcarrier
frequency is evaluated out of FSCPLL increment.

If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.

handbook, full pagewidth

128

72 74

0 1

RTCI

HPLL

increment

(1)

FSCPLL increment

(2)

HIGH-to-LOW transition

count start

4 bits

reserved

valid

sample

invalid

sample

not used in SAA7120H/21H

3 bits

reserved

8/LLC

MBH789

LOW

time slot:

(3)

(4)

(6)

(7)

(8)

(5)

Fig.9 RTCI timing.

(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.

(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.

(3) Sequence bit: PAL: 0 = (R

Y) line normal, 1 = (R

Y) line inverted; NTSC: 0 = no change.

(4) Reset bit: only from SAA7111 and SAA7112 decoder.

(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.

(6) Odd/even bit: odd_even from external.

(7) Colour detection: 0 = no colour detected, 1 = colour detected.

(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

8.2

Teletext timing

Time t

is the time needed to interpolate input data TTX

and insert it into the CVBS and Y output signal, such that
it appears at t

TTX

= 9.78

s (PAL) or t

TTX

= 10.5

(NTSC) after the leading edge of the horizontal
synchronization pulse.

Time t

is the pipeline delay time introduced by the

source that is gated by TTXRQ in order to deliver TTX
data. This delay is programmable by register TTXHD. For
every active HIGH state at output pin TTXRQ, a new
teletext bit must be provided by the source.

Since the beginning of the pulses representing the TTXRQ
signal and the delay between the rising edge of TTXRQ
and valid teletext input data are fully programmable
(TTXHS and TTXHD), the TTX data is always inserted at
the correct position after the leading edge of outgoing
horizontal synchronization pulse.

Time t

TTXWin

is the internally used insertion window for

TTX data; it has a constant length that allows insertion of
360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL),
296 teletext bits at a text data rate of 5.7272 Mbits/s (WST)
or 288 teletext bits at a text data rate of 5.7272 Mbits/s
(NABTS). The insertion window is not opened if the control
bit TTXEN is logic 0.

Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.

handbook, full pagewidth

tTTXWin

tTTX

tPD

tFD

CVBS/Y

TTX

TTXRQ

textbit #:

10 11

18 19 20

MBH788

Fig.10 Teletext timing.

2002

Oct

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

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APPLICA

TION INFORMA

TION

handbook, full pagewidth

(1)

4.7

AGND

CVBS

DAC1

DAC2

DAC3

VDDA3

UCVBS
1.23 V (p-p)

(2)

AGND

UY
1.00 V (p-p)

(2)

MBH786

AGND

DGND

UC
0.89 V (p-p)

(2)

AGND

VDDA2

32, 33

5, 18, 38

VDDA1

3.3 V analog

3.3 V digital

VSSD1, VSSD2, VSSD3

VDDD1, VDDD2, VDDD3

VSSA1, VSSA2

6, 17, 39

XTALI

XTALO

10 pF

use one capacitor
for each VDDD

(1)

VDDA4

(1)

0.1

AGND

0.1

AGND

0.1

DGND

0.1

1 nF

3rd harmonic

27.0 MHz

digital

inputs and

outputs

SAA7120H
SAA7121H

Fig.11 Application circuit.

(1) Typical value.

(2) For

100

colour bar.

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

10 PACKAGE OUTLINE

UNIT

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

0.25
0.05

1.85
1.65

0.25

0.40
0.20

0.25
0.14

10.1

9.9

0.8

1.3

12.9
12.3

1.2
0.8

0.15

0.1

0.15

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.95
0.55

SOT307-2

95-02-04
97-08-01

(1)

10.1

9.9

12.9
12.3

1.2
0.8

Z E

detail X

(A )

pin 1 index

2.5

5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

max.

2.10

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

11 SOLDERING

11.1

Introduction to soldering surface mount
packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

11.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 220

C for

thick/large packages, and below 235

C for small/thin

packages.

11.3

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

11.4

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

11.5

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. For more detailed information on the BGA packages refer to the

"(LF)BGA Application Note" (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

(1)

SOLDERING METHOD

WAVE

REFLOW

(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA

not suitable

suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

(3)

suitable

PLCC

(4)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(4)(5)

suitable

SSOP, TSSOP, VSO

not recommended

(6)

suitable

2002 Oct 11

Philips Semiconductors

Product specification

Digital video encoder

SAA7120H; SAA7121H

12 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

III

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

13 DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

14 DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

SCA74

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

753505/02/pp

Date of release:

2002 Oct 11

Document order number:

9397 750 09829

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7121H

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7121H