Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

Version 0.1

1996 Sep 24

GENERAL DESCRIPTION

PR31500 Processor is a single-chip, low-cost, integrated embedded
processor consisting of MIPS R3000 core and system support logic
to interface with various types of devices.

PR31500 consists of a MIPS R3000 RISC CPU with 4 KBytes of
instruction cache memory and 1 KByte of data cache memory, plus
integrated functions for interfacing to numerous system components
and external I/O modules. The R3000 RISC CPU is also augmented
with a multiply/accumulate module to allow integrated DSP
functions, such as a software modem for high-performance standard
data and fax protocols.

The PR31500 processor can support both Little and Big Endian
operating systems. In addition the PR31500 provides a memory
management unit with an on-chip Translation Look aside Buffer
(TLB) for very fast virtual to physical address translation.

PR31500 also contains multiple DMA channels and a
high-performance and flexible Bus Interface Unit (BIU) for providing
an efficient means for transferring data between external system
memory, cache memory, the CPU core, and external I/O modules.
The types of external memory devices supported include dynamic
random access memory (DRAM), synchronous dynamic random
access memory (SDRAM), static random access memory (SRAM),
Flash memory, read-only memory (ROM), and expansion cards
(e.g., PCMCIA). PR31500 also contains a System Interface Module
(SIM) containing integrated functions for interfacing to numerous
external I/O modules such as liquid crystal displays (LCDs), the
UCB1100 (which handles most of the analog functions of the
system, including sound and telecom codecs and touchscreen
ADC), ISDN/high-speed serial, infrared, wireless peripherals, etc.
Lastly, PR31500 contains support for implementation of power
management, whereby various PR31500 internal modules and
external subsystems can be individually (under software control)
powered up and down.

Figure 1 shows an External Block Diagram of PR31500.

FEATURES

32-bit R3000 RISC static CMOS CPU

4 KByte instruction cache

1 KByte data cache

Multiply/accumulator Instruction

R3000A memory management unit with on-chip TLB

Supports Big/Little Endian operating systems

On-chip peripherals with individual power-down

Multi-channel DMA controller

Bus interface unit

Memory controller for ROM, Flash, RAM, DRAM, SDRAM,

SRAM, and PCMCIA

Power management module

Video module

Real-time clock 32.760KHz reference

High-speed serial interface

Infrared module

Dual-UART

SPI bus

3.3V supply voltage

208-pin LQFP (Low profile quad flat pack)

40MHz operation frequency

ORDERING INFORMATION

PART NUMBER

TEMPERATURE RANGE (

C) AND PACKAGE

FREQUENCY

(MHz)

DRAWING NUMBER

PR31500ABC

0 to +70, 208-pin Low Profile Quad Flat Pack

LQFP208

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

ООООООООООООООООООООО

R3000 RISC

CPU Core

ICache

4KByte

DCache

1KByte

Bus Interface Unit (BIU) Module

(S)DRAM/PCMCIA/ROM

Data

Addr

CHI Module

Addr

Data

Addr

Control

to UCB1100

to LCD

to high

speed serial

to IR

Timer Module

(+ RTC)

IR Module

UART Module

(dual UART)

MAC

to UART

Power Module

SPI Module

to Power

Supply

IO Module

to general

purpose I/O

32 KHz

SYSCLK

Interrupt Module

System Interface Module (SIM)

Memory

CPU

Module

DA
T

ADDR

System Interface Unit (SIU) Module

Arbitration/DMA/AddrDecode

Video Module

SIB Module

MMU

Clock Module

SN00162

Figure 1. PR31500 Block Diagram

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

OVERVIEW

Each of the on-chip peripherals consist of:

BIU Module

System memory and PR31500 Bus Interface Unit (BIU)

supports up to 2 banks of physical memory

supports self-refreshing DRAM and SDRAM

programmable parameters for each bank of DRAM or SDRAM

(row/column address configuration, refresh, burst modes, etc.)

programmable chip select memory access

4 programmable (size, wait states, burst mode control) memory

device and general purpose chip selects

available for system ROM, SRAM, Flash

available for external port expansion registers

supports up to 2 identical full PCMCIA ports

PR31500 and UCB1100 provide the control signals and accepts

the status signals which conform to the PCMCIA version 2.01
standard

appropriate connector keying and level-shifting buffers required

for 3.3V versus 5V PCMCIA interface implementations

SIU Module

multi-channel 32-bit DMA controller and System Interface Unit
(SIU)

independent DMA channels for video, SIB to/from UCB1100
audio/telecom codecs, high-speed serial port, IR UART, and
general purpose UART

address decoding for submodules within System Interface Module
(SIM)

CPU Module

R3000 RISC central processing unit core

full 32-bit operation (registers, instructions, addresses)

32 general purpose 32-bit registers; 32-bit program counter

MIPS RISC Instruction Set Architecture (ISA) supported

on-chip cache

4 KByte direct-mapped instruction cache (I-cache)

physical address tag and valid bit per cache line

programmable burst size

instruction streaming mode supported

1 KByte data cache (D-cache)

physical address tag and valid bit per cache line

programmable burst size

write-through

cache address snoop mode supported for DMA

4-level deep write buffer

Memory Management Unit

MIPS R3000A MMU contains on-chip TLB with:

64 bit wide entries

fully associative

2 entry micro TLB for very fast instruction address translation

Instruction address translation accesses full TLB after micro
TLB miss

Data address translation accesses full TLB

high-speed multiplier/accumulator

on-chip hardware multiplier

supports 16x16 or 32x32 multiplier operations, with 64-bit

accumulator

existing multiply instructions are enhanced and new multiply

and add instructions are added to R3000 instruction set to
improve the performance of DSP applications

CPU interface

handles data bus, address bus, and control interface between

CPU core and rest of PR31500 logic

Clock Module

PR31500 supports system-wide single crystal configuration,
besides the 32 KHz RTC XTAL (reduces cost, power, and board
space)

common crystal rate divided to generate clock for CPU, video,
sound, telecom, UARTs, etc.

external system crystal rate is vendor-dependent

independent enabling or disabling of individual clocks under
software control, for power management

CHI Module

high-speed serial Concentration Highway Interface (CHI) contains
logic for interfacing to external full-duplex serial
time-division-multiplexed (TDM) communication peripherals

supports ISDN line interface chips and other PCM/TDM serial
devices

CHI interface is programmable (number of channels, frame rate,
bit rate, etc.) to provide support for a variety of formats

supports data rates up to 4.096 Mbps

independent DMA support for CHI receive and transmit

Interrupt Module

contains logic for individually enabling, reading, and clearing all
PR31500 interrupt sources

interrupts generated from internal PR31500 modules or from edge
transitions on external signal pins

IO Module

contains support for reading and writing the 7 bi-directional
general purpose IO pins and the 32 bi-directional multi-function IO
pins

each IO port can generate a separate positive and negative edge
interrupt

independently configurable IO ports allow PR31500 to support a
flexible and wide range of system applications and configurations

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

IR Module

IR consumer mode

allows control of consumer electronic devices such as stereos,

TVs, VCRs, etc.

programmable pulse parameters

external analog LED circuitry

IRDA communication mode

allows communication with other IRDA devices such as FAX

machines, copiers, printers, etc.

supported by UART module within PR31500

external analog receiver preamp and LED circuitry

data rate = up to 115 Kbps at 1 meter

IR FSK communication mode

supported by UART module within PR31500

external analog IR chip(s) perform frequency modulation to

generate the desired IR communication mode protocol

data rate = up to 36000 bps at 3 meters

carrier detect state machine

periodically enables IR receiver to check if a valid carrier is

present

Power Module

power-down modes for individual internal peripheral modules

serial (SPI port) power supply control interface supported

power management state machine has 4 states: RUNNING,
DOZING, SLEEP, and COMA

Serial Interconnect Bus (SIB) Module

PR31500 contains holding and shift registers to support the serial
interface to the UCB1100 and/or other optional codec devices

interface compatible with slave mode 3 of Crystal CS4216 codec

synchronous, frame-based protocol

PR31500 always master source of clock and frame frequency and
phase; programmable clock frequency

each SIB frame consists of 128 clock cycles, further divided into 2
subframes or words of 64 bits each (supports up to 2 devices
simultaneously)

independent DMA support for audio receive and transmit, telecom
receive and transmit

supports 8-bit or 16-bit mono telecom formats

supports 8-bit or 16-bit mono or stereo audio formats

independently programmable audio and telecom sample rates

CPU read/write registers for subframe control and status

System Peripheral Interface (SPI) Module

provides interface to SPI peripherals and devices

full-duplex, synchronous serial data transfers (data in, data out,
and clock signals)

PR31500 supplies dedicated chip select and interrupt for an SPI
interface serial power supply

8-bit or 16-bit data word lengths for the SPI interface

programmable SPI baud rate

Timer Module

Real Time Clock (RTC) and Timer

40-bit counter (30.517

sec granularity);

maximum uninterrupted time = 388.36 days

40-bit alarm register (30.517

sec granularity)

16-bit periodic timer (0.868

sec granularity);

maximum timeout = 56.8 msec

interrupts on alarm, timer, and prior to RTC roll-over

UART Module

2 independent full-duplex UARTs

programmable baud rate generator

UART-A port used for serial control interface to external IR
module

UART-B port used for general purpose serial control interface

UART-A and UART-B DMA support for receive and transmit

Video Module

bit-mapped graphics

supports monochrome, grey scale, or color modes

time-based dithering algorithm for grey scale and color modes

supports multiple screen sizes

supports split and non-split displays

variable size and relocatable video buffer

DMA support for fetching image data from video buffer

Little/Big Endian Configuration

The PR31500 can be configures as a Big Endian or as a Little
Endian processor based on the /LB endian pin at power-up.

The byte ordering is as follows:

LITTLE ENDIAN

BIG ENDIAN

D[31:24]

D[7:0]

D[23:16]

D[15:8]

D[23:16]

D[7:0]

D[31:24]

/CAS3

/CAS0

/CAS2

/CAS1

/CAS2

/CAS0

/CAS3

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

PIN CONFIGURATION

208

104

105

156

157

208-PIN

PLASTIC

QUAD FLAT PACK

TOP VIEW

Pin

Function

D(0)

[D(24)]

D(1)

[D(25)]

D(2)

[D(26)]

D(3)

[D(27)]

D(4)

[D(28)]

D(5)

[D(29)]

D(6)

[D(30)]

D(7)

[D(31)]

D(8)

[D(16)]

D(9)

[D(17)]

D(10)

[D(18)]

D(11)

[D(19)]

D(12)

[D(20)]

D(13)

[D(21)]

D(14)

[D(22)]

D(15)

[D(23)]

/LB endian

MFIO(1)

SIBMCLK

SIBSCLK

SIBSYNC

SIBDIN

SIBDOUT

SIBIRQ

MFIO(0)

IO(6)

IO(50

chiclk

chifs

chidin

chidout

Pin

Function

RXD

TXD

IO(4)

57
58

IRIN

IROUT

CARDET

TXPWR

IO(3)

IO(2)

SPICLK

SPIIN

SPIOUT

TESTCPU

TESTIN

VIDDONE

TESTSIU

BC32K

C32KIN

C32KOUT

PWRCS

PWRINT

PWROK

85
86

ONBUTN

/PON

/CPURES

DISPON

FRAME

LOAD

VDAT(0)

VDAT(1)

100

VDAT(2)

101

VDAT(3)

102

103

IO(1)

104

Pin

Function

105

/CARD2WAIT

106

/CARD2CSH

107

/CARD2CSL

108

IO(0)

109

110

/IORD

111

/IOWR

112

/CARDREG

113

/CARD1WAIT

114

115

MFIO(2)

116

117

/CARD1CSL

118

/CARD1CSH

119

120

/MCS3

121

/MCS2

122

/MCS1

123

/MCS0

124

/CS3

125

/CS2

126

/CS1

127

128

SYSCLKIN

129

SYSCLKOUT

130

131

132

133

D(31)

[D(7)]

134

D(30)

[D(6)]

135

136

D(29)

[D(5)]

137

138

D(28)

[D(4)]

139

D(27)

[D(3)]

140

141

D(26)

[D(2)]

142

143

D(25)

[D(1)]

144

145

D(24)

[D(0)]

146

D(23)

[D(15)]

147

148

D(22)

[D(14)]

149

150

D(21)

[D(13)]

151

152

D(20)

[D(12)]

153

D(19)

[D(11)]

154

155

D(18)

[D(10)]

156

Pin

Function

157

D(17)

[D(9)]

158

159

D(16)

[D(8)]

160

161
162

/CS0

163

/RD

164

165

166

/DGRNT

167

/DREQ

168

ALE

169

/WE

170

171

A(12)

172

A(11)

173

174

A(10)

175

A(9)

176

177

A(8)

178

A(7)

179

180

A(6)

181

A(5)

182

183

A(4)

184

185

A(3)

186

A(2)

187

188

A(1)

189

A(0)

190

191

192

/DCS0

193

/RAS1

194

/RAS0

195

/CAS3

[/CAS0]

196

197

/CAS2

[/CAS1]

198

/CAS1

[/CAS2]

199

/CAS0

[/CAS3]

200

201

202

DCKE

203

204

DCLKIN

205

DCLKOUT

206

207

DQMH

208

DQML

NOTE:

[ ] indicates the signal name in the Little Endian mode.

SN00164

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

PIN DESCRIPTIONS

Overview

The PR31500 processor contains 208 pins consisting of input, output, bi-directional, and power and ground pins. These pins are used to
support various functions. The following sections will describe the function of each pin including any special power-down considerations for
each pin.

Pins

The PR31500 PROCESSOR contains 208 total pins, consisting of 136 signal pins, 4 spare pins, 34 power pins, and 34 ground pins. Of the 136
signal pins, 32 of them are multi-function and can be independently programmed either as IO ports or for an alternate standard/normal function.
As an IO port, any of these pins can be programmed as an input or output port, with the capability of generating a separate positive and
negative edge interrupt. See Section 2.3 for a summary of the multi-function IO ports versus their standard functions.

PIN #

NAME

TYPE

NAME AND FUNCTION

Memory Pins

D(31:0)

I/O

These pins are the data bus for the system. 8-bit SDRAMs should be connected to bits 7:0 and
16-bit SDRAMs and DRAMs should be connected to bits 15:0. All other 16-bit ports should be
connected to bits 31:16. Of course, 32-bit ports should be connected to bits 31:0. These pins are
normally outputs and only become inputs during reads, thus no resistors are required since the
bus will only float for a short period of time during bus turn-around.

A(12:0)

These pins are the address bus for the system. The address lines are multiplexed and can be
connected directly to SDRAM and DRAM devices. To generate the full 26-bit address for static
devices, an external latch must be used to latch the signals using the ALE signal. For static
devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly
connected from PR31500's address bus) are held afterward by PR31500 processor for the
remainder of the address bus cycle.

168

ALE

This pin is used as the address latch enable to latch A(12:0) using an external latch, for generating
the upper address bits 25:13.

163

/RD

This pin is used as the read signal for static devices. This signal is asserted for reads from
/MCS3-0, /CS3-0, /CARD2CS and /CARD1CS for memory and attribute space, and for reads from
PR31500 processor accesses if SHOWPR31500 is enabled (for debugging purposes).

169

/WE

This pin is used as the write signal for the system. This signal is asserted for writes to /MCS3-0,
/CS3-0, /CARD2CS and /CARD1CS for memory and attribute space, and for writes to DRAM and
SDRAM.

199

/CAS0 (/WE0)

This pin is used as the CAS signal for SDRAMs, the CAS signal for D(7:0) for DRAMs, and the
write enable signal for D(7:0) for static devices.

198

/CAS1 (/WE1)

This pin is used as the CAS signal for D(15:8) for DRAMs and the write enable signal for D(15:8)
for static devices.

197

/CAS2 (/WE2)

This pin is used as the CAS signal for D(23:16) for DRAMs and the write enable signal for
D(23:16) for static devices.

195

/CAS3 (/WE3)

This pin is used as the CAS signal for D(31:24) for DRAMs and the write enable signal for
D(31:24) for static devices.

194

/RAS0

This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs.

193

/RAS1 (/DCS1)

This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1
DRAMs.

192

/DCS0

This pin is used as the chip select signal for Bank0 SDRAMs.

202

DCKE

This pin is used as the clock enable for SDRAMs.

204

DCLKIN

This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data
input when reading from SDRAM and DRAM devices.

205

DCLKOUT

This pin is the (nominal) 73.728 MHz clock for the SDRAMs.

207

DQMH

This pin is the upper data mask for a 16-bit SDRAM configuration.

208

DQML

This pin is the lower data mask for a 16-bit SDRAM or 8-bit SDRAM configuration.

124126,
162

/CS30

These pins are the Chip Select 3 through 0 signals. They can be configured to support either 32-bit
or 16-bit ports.

120123

/MCS30

These pins are the MagicCard Chip Select 3 through 0 signals. They only support 16-bit ports.

106, 107

/CARD2CSH,L

These pins are the Chip Select signals for PCMCIA card slot 2.

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

PIN #

NAME AND FUNCTION

TYPE

NAME

Memory Pins (continued)

117, 118

/CARD1CSH,L

These pins are the Chip Select signals for PCMCIA card slot 1.

112

/CARDREG

This pin is the /REG signal for the PCMCIA cards.

110

/CARDIORD

This pin is the /IORD signal for the PCMCIA IO cards.

111

/CARDIOWR

This pin is the /IOWR signal for the PCMCIA IO cards.

115

/CARDDIR

This pin is used to provide the direction control for bi-directional data buffers used for the PCMCIA
slot(s). This signal will assert whenever /CARD2CSH or /CARD2CSL or /CARD1CSH or
/CARD1CSL is asserted and a read transaction is taking place.

105

/CARD2WAIT

This pin is the card wait signal from PCMCIA card slot 2.

113

/CARD1WAIT

This pin is the card wait signal from PCMCIA card slot 1.

Bus Arbitration Pins

167

/DREQ

This pin is used to request external arbitration. If the TESTSIU signal is high and the TESTSIU
function has been enabled, then once /DGRNT is asserted, external logic can initiate reads or
writes to PR31500 processor registers by driving the appropriate input signals. If the TESTSIU
signal is low or the TESTSIU function has not been enabled, then PR31500 memory transactions
are halted and certain memory signals will be tri-stated when /DGRNT is asserted in order to allow
an external master to access memory.

166

/DGRNT

This pin is asserted in response to /DREQ to inform the external test logic or bus master that it can
now begin to drive signals.

Clock Pins

128

SYSCLKIN

This pin should be connected along with SYSCLKOUT to an external crystal which is the main
PR31500 clock source.

129

SYSCLKOUT

This pin should be connected along with SYSCLKIN to an external crystal which is the main
PR31500 clock source.

C32KIN

This pin along with C32KOUT should be connected to a 32.768 KHz crystal.

C32KOUT

This pin along with C32KIN should be connected to a 32.768 KHz crystal.

BC32K

This pin is a buffered output of the 32.768 KHz clock.

CHI Pins

CHIFS

I/O

This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes.

As an output, this pin allows PR31500 to be the master CHI sync source. As an input, this pin
allows an external peripheral to be the master CHI sync source and the PR31500 CHI module will
slave to this external sync.

CHICLK

I/O

This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output,
this pin allows PR31500 to be the master CHI clock source. As an input, this pin allows an
external peripheral to be the master CHI clock source and the PR31500 CHI module will slave to
this external clock.

CHIDOUT

This pin is the CHI serial data output signal.

CHIDIN

This pin is the CHI serial data input signal.

IO Pins

46, 107,
47, 108,
56, 64,
64

IO(6:0)

I/O

These pins are general purpose input/output ports. Each port can be independently programmed

as an input or output port. Each port can generate a separate positive and negative edge interrupt.

Each port can also be independently programmed to use a 16 to 24 msec debouncer.

30, 45

MFIO(1:0)

I/O

These pins are multi-function input/output ports. Each port can be independently programmed as
an input or output port, or can be programmed for multi-function use to support vendor-dependent
test signals (for debugging purposes only). Each port can generate a separate positive and
negative edge interrupt. Note that 30 other multi-function pins are available for usage as
multi-function input/output ports. These pins are named after their respective standard/normal
function and are not listed here.

Endian Processor Pin

/LB endian

Little/Big Endian. This pin, when pulled Low at power-up, configures the PR31500 as a Little
Endian. When this pin is pulled High at power-up, it configures the PR31500 as a Big Endian
processor.

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

PIN #

NAME AND FUNCTION

TYPE

NAME

Reset Pins

/CPURES

This pin is used to reset the CPU core. This pin should be connected to a switch for initiating a
reset in the event that a software problem might hang the CPU core. The pin should also be pulled
up to VSTANDBY through an external pull-up resistor.

/PON

This pin serves as the Power On Reset signal for PR31500. This signal must remain low when
VSTANDBY is asserted until VSTANDBY is stable. Once VSTANDBY is asserted, this signal
should never go low unless all power is lost in the system.

Power Supply Pins

ONBUTN

This pin is used as the On Button for the system. Asserting this signal will cause PWRCS to set to
indicate to the System Power Supply to turn power on to the system. PWRCS will not assert if the
PWROK signal is low.

PWRCS

This pin is used as the chip select for the System Power Supply. When the system is off, the
assertion of this signal will cause the System Power Supply to turn VCCDRAM and VCC3 on to
power up the system. The Power Supply will latch SPI commands on the falling edge of PWRCS.

PWROK

This pin provides a status from the System Power Supply that there is a good source of power in
the system. This signal typically will be asserted if there is a Battery Charger supplying current or
if the Main Battery is good and the Battery Door is closed. If PWROK is low when the system is
powered off, PWRCS will not assert as a result of the user pressing the ONBUTN or an interrupt
attempting to wake up the system. If the device is on when the PWROK signal goes low, the
software will immediately shut down the system since power is about to be lost. When PWROK
goes low, there must be ample warning so that the software can shut down the system before
power is actually lost.

PWRINT

This pin is used by the System Power Supply to alert the software that some status has changed
in the System Power Supply and the software should read the status from the System Power
Supply to find out what has changed. These will be low priority events, unlike the PWROK status,
which is a high priority emergency case.

VCC3

This pin provides the status of the power supply for the ROM, UCB1100, system buffers, and other
transient components in the system. This signal will be asserted by the System Power Supply
when PWRCS is asserted, and will always be turned off when the system is powered down.

SIB Pins

SIBDIN

This pin contains the input data shifted from UCB1100 and/or external codec device.

SIBDOUT

This pin contains the output data shifted to UCB1100 and/or external codec device.

SIBSCLK

This pin is the serial clock sent to UCB1100 and/or external codec device. The programmable
SIBSCLK rate is derived by dividing down from SIBMCLK.

SIBSYNC

This pin is the frame synchronization signal sent to UCB1100 and/or external codec device. This
frame sync is asserted for one clock cycle immediately before each frame starts and all devices
connected to the SIB monitor SIBSYNC to determine when they should transmit or receive data.

SIBIRQ

This pin is a general purpose input port used for the SIB interrupt source from UCB1100. This
interrupt source can be configured to generate an interrupt on either a positive and/or negative
edge.

SIBMCLK

I/O

This pin is the master clock source for the SIB logic. This pin is available for use in one of two
modes. First, SIBMCLK can be configured as a high-rate output master clock source required by
certain external codec devices. In this mode all SIB clocks are synchronously slaved to the main
PR31500 system clock CLK2X. Conversely, SIBMCLK can be configured as an input slave clock
source. In this mode, all SIB clocks are derived from an external SIBMCLK oscillator source,
which is asynchronous with respect to CLK2X. Also, for this mode, SIBMCLK can still be
optionally used as a high-rate master clock source required by certain external codec devices.

SPI Pins

SPICLK

This pin is used to clock data in and out of the SPI slave device.

SPIOUT

This pin contains the data that is shifted into the SPI slave device.

SPIIN

This pin contains the data that is shifted out of the SPI slave device.

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

PIN #

NAME AND FUNCTION

TYPE

NAME

UART and IR Pins

TXD

This pin is the UART transmit signal from the UARTA module.

RXD

This pin is the UART receive signal to the UARTA module.

IROUT

This pin is the UART transmit signal from the UARTB module or the Consumer IR output signal if
Consumer IR mode is enabled.

IRIN

This pin is the UART receive signal to the UARTB module.

RXPWR

This pin is the receiver power output control signal to the external communication IR analog
circuitry.

CARDET

This pin is the carrier detect input signal from the external communication IR analog circuitry.

Video Pins

FRAME

This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is
used by the LCD to return it's pointers to the top of the display. The Video Module asserts FRAME
after all the lines of the LCD have been shifted and transferred, producing a full frame of display.

This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected
to a DC voltage, the DF signal is used by the LCD to alternate the polarity of the row and column
voltages used to turn the pixels on and off. The DF signal can be configured to toggle on every
frame or can be configured to toggle every programmable number of LOAD signals.

LOAD

This pin is the line synchronization pulse signal between the Video Module and the LCD, and is
used by the LCD to transfer the contents of it's horizontal line shift register to the LCD panel for
display. The Video Module asserts LOAD after an entire horizontal line of data has been shifted
into the LCD.

This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of
CP and sampled by the LCD on the falling edge of CP.

101, 100,
99, 98

VDAT(3:0)

These pins are the data for the LCD. These signals are directly connected to the LCD for 4-bit
non-split displays. For 4-bit split and 8-bit non-split displays, an external register is required to
demultiplex the 4-bit data into the desired 8 parallel data lines needed for the LCD.

DISPON

This pin is the display-on enable signal for the LCD.

Test Pins

TESTSIU

This pin allows external logic to initiate read or write transactions to PR31500 registers. The
TESTSIU mode is enabled by toggling this signal after the device has powered up. Once the
function is enabled, if the TESTSIU pin is high when the bus is arbitrated (using /DREQ and
/DGRNT), then external logic can initiate read and write transactions to PR31500 registers. This
pin is used for debugging purposes only.

TESTCPU

This pin allows numerous internal CPU core signals to be brought to external PR31500 pins, in
place of the normal signals assigned to these pins. The CPU core signals assigned to their
respective pins during TESTCPU mode are vendor-dependent. The TESTCPU mode is enabled
by asserting this TESTCPU signal, and this function is provided for generating test vectors for the
CPU core. This pin is used for debugging purposes only.

TESTIN

This pin is reserved for vendor-dependent use. This pin is used for debugging purposes only.

VIDDONE

This signal is used to synchronize UCB1100 to read touchscreen input, when there is no video
data shifted into LCD panel.

Spare Pins

NC41

Connect

These pins are reserved for future use and should be left unconnected.

Reserved.

32, 31

Reserved.

Power Supply Pins

(34 each)

+3.3V

These pins are the power pins for PR31500 and should be connected to the digital +3.3V power
supply VSTANDBY.

(34 each)

GND

These pins are the ground pins for PR31500 and should be connected to digital ground.
NOTE: For some vendor-dependent implementations of PR31500, pin 131 may be used for a filter
capacitor for the SYSCLK oscillator (capacitor connected between pin 131 and digital ground).

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

= 0V

SYMBOL

PARAMETER

LIMITS

UNIT

Power supply voltage

0.5 to 4.5

Input voltage

0.5 to V

+ 0.5

stg

Storage temperature range

55 to +125

Maximum dissipation (T

amb

= 70

RECOMMENDED OPERATING CONDITION

= 0V

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Power supply voltage

3.0

3.3

3.6

Input voltage

opr

Operating temperature range

DC ELECTRICAL CHARACTERISTICS

amb

= 0 to +70

C, V

= 3.3

0.3V.

SYMBOL

PARAMETER

CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Operating current

= V

or V

; V

= MAX

= I

= 0

110

TBD

DDS

Static current

= V

or V

; V

= MAX

= I

= 0

100

Input leakage current

= MAX; V

= V

IH1

High level input voltage

= 3.6V

0.8

+ 0.3

IL1

Low level input voltage

= 3.0V

0.3

0.2

IH2

High level input voltage

= 3.6V

2.4

+ 0.3

IL2

Low level input voltage

= 3.0V

0.3

0.6

OH1

High level output voltage

= 3.0; I

= 4mA

0.6

OL1

Low level output voltage

= 3.0; I

= 4mA

+ 0.4

OH2

High level output voltage

= 3.0; I

= 8mA

0.6

OL2

Low level output voltage

= 3.0; I

= 8mA

+ 0.4

OH3

High level output voltage

= 3.0; I

= 16mA

0.6

OL3

Low level output voltage

= 3.0; I

= 16mA

+ 0.4

OH4

High level output voltage

= 3.0; I

= 24mA

0.6

OL4

Low level output voltage

= 3.0; I

= 24mA

+ 0.4

IHP

Input current (pull-down resistor)

= MAX; V

= V

120

NOTES:
1. SYSVLKIN
2. Other inputs
3. D[31:0], /RAS0, /RAS1, /DCS0, /DCKE, DQMH, DQML, /DREQ, /DGRNT, BC32K, VDAT[3:0], CP, LOAD, DF, FRAME, DISPON, VIDDONE,

PWRCS, TXD, RXD, /CS0

3, /MCS0

3, CHIFS, CHICLK, CHIDOUT, CHIDIN, IO[6:0], SPICLK, SPIOUT, SPIIN, SIBSYNC, SIBOUT,

SIBMCLK, SIBCLK, RXPWR, IROUT, /CRAD1WAIT, /CARD2WAIT, MIOX[2:0]

4. A[12:0], ALE, /RD, /WE /CAS0

3, /CARDREG, /IOWR, /CARD1CSL, /CARD1CSH, /CARD2CSL, /CARD2CSH

5. DCLKOUT

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

MEMORY INTERFACE

amb

= 0 to +70

C, V

= 3.3

0.3V, External Capacitance = 40pF

ITEM

PARAMETER

RISING/FALLING

LIMITS

UNIT

ITEM

PARAMETER

RISING/FALLING

MIN

MAX

UNIT

DCLKOUT high time

5.4

DCLKOUT low time

5.4

DCLKOUT period

13.5

Delay DCLKOUT to ALE

Rising

Delay DCLKOUT to ALE

Falling

Delay DCLKOUT to A[12:0]

Delay DCLKOUT to D[31:16]

Delay DCLKOUT to D[15:0]

1.5

Delay DCLKOUT to /CS30

Rising

Delay DCLKOUT to /CS30

Falling

Delay DCLKOUT to /RD

Risng

Delay DCLKOUT to /RD

Falling

Delay DCLKOUT to /WE

Rising

Delay DCLKOUT to /WE

Falling

Delay DCLKOUT to /SAS30

Rising

1.5

Delay DCLKOUT to /SAS30

Falling

1.5

Delay DCLKOUT to /CARDxCSx

Rising

Delay DCLKOUT to /CARDxCSx

Falling

Delay DCLKOUT to /CARDDIR

Rising

Delay DCLKOUT to /CARDDIR

Falling

Delay DCLKOUT to /CARDREG

Rising

Delay DCLKOUT to /CARDREG

Falling

Delay DCLKOUT to /IORD

Rising

Delay DCLKOUT to /IORD

Falling

Delay DCLKOUT to /IOWR

Rising

Delay DCLKOUT to /IOWR

Falling

Delay DCLKOUT to /RAS0

Rising

Delay DCLKOUT to /RAS0

Falling

Delay DCLKOUT to /RAS1

Rising

1.5

Delay DCLKOUT to /RAS1

Falling

1.5

Delay DCLKOUT to DQMH/L

Rising

1.5

Delay DCLKOUT to DQMH/L

Falling

1.5

Delay DCLKOUT to /DCS0

Rising

1.5

Delay DCLKOUT to /DCS0

Falling

1.5

Delay DCLKOUT to DCKE

Rising

1.5

Delay DCLKOUT to DCKE

Falling

1.5

Delay DCLKOUT to /MCS30

Rising

Delay DCLKOUT to /MCS30

Falling

D[31:16] to DCLKIN Setup time

D[31:16] to DCLKIN Hold time

D[15:0] to DCLKIN Setup time

D[15:0] to DCLKIN Hold time

1.5

DCLKOUT to DCLKIN Board Delay time

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

CHI

amb

= 0 to +70

C, V

= 3.3

0.3V, External Capacitance = 40pF

ITEM

PARAMETER

RISING/FALLING

LIMITS

UNIT

ITEM

PARAMETER

RISING/FALLING

MIN

MAX

UNIT

CHICLK high time

100

CHICLK low time

100

CHICLK period

225

Delay CHICLK Rising to CHIDOUT (Master)

Rising

Delay CHICLK Rising to CHIDOUT (Master)

Falling

Delay CHICLK Falling to CHIDOUT (Master)

Rising

Delay CHICLK Falling to CHIDOUT (Master)

Falling

Delay CHICLK Rising to CHIFS (Master)

Rising

Delay CHICLK Rising to CHIFS (Master)

Falling

Delay CHICLK Falling to CHIFS (Master)

Rising

Delay CHICLK Falling to CHIFS (Master)

Falling

Delay CHICLK Rising to CHIDOUT (Slave)

Rising

Delay CHICLK Rising to CHIDOUT (Slave)

Falling

Delay CHICLK Falling to CHIDOUT (Slave)

Rising

Delay CHICLK Falling to CHIDOUT (Slave)

Falling

Delay CHICLK Rising to CHIFS (Slave)

Rising

Delay CHICLK Rising to CHIFS (Slave)

Falling

Delay CHICLK Falling to CHIFS (Slave)

Rising

Delay CHICLK Falling to CHIFS (Slave)

Falling

CHIDIN to CHICLK Rising Setup time (Master)

CHIDIN to CHICLK Rising Hold time (Master)

CHIDIN to CHICLK Falling Setup time (Master)

CHIDIN to CHICLK Falling Hold time (Master)

CHIFS to CHICLK Rising Setup time (Slave)

CHIFS to CHICLK Rising Hold time (Slave)

CHIFS to CHICLK Falling Setup time (Slave)

CHIFS to CHICLK Falling Hold time (Slave)

CHIDIN to CHICLK Rising Setup time (Slave)

CHIDIN to CHICLK Rising Hold time (Slave)

CHIDIN to CHICLK Falling Setup time (Slave)

CHIDIN to CHICLK Falling Hold time (Slave)

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

SIB

amb

= 0 to +70

C, V

= 3.3

0.3V, External Capacitance = 40pF

ITEM

PARAMETER

RISING/FALLING

LIMITS

UNIT

ITEM

PARAMETER

RISING/FALLING

MIN

MAX

UNIT

SIBMCLK high time

SIBMCLK low time

SIBMCLK period

Delay SIBMCLK to SIBSCLK

Rising

Delay SIBMCLK to SIBSCLK

Falling

Delay SIBSCLK Rising to SIBSYNC

Rising

Delay SIBSCLK Rising to SIBSYNC

Falling

Delay SIBSCLK Rising to SIBDOUT

Rising

Delay SIBSCLK Rising to SIBDOUT

Falling

SIBDIN to SIBSCLK Rising Setup time

SIBDIN to SIBSCLK Rising Hold time

SIB TIMING DIAGRAMS

SIBMCLK

SIBSCLK

SN00175

Figure 8. SIB CLK Timing

SIBSCLK

SIB

OUTPUTS

SIBDIN

SN00176

Figure 9. SIB Timing

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

SPI

ITEM

PARAMETER

RISING/FALLING

LIMITS

UNIT

ITEM

PARAMETER

RISING/FALLING

MIN

MAX

UNIT

SPIMCLK high time

120

SPICLK low time

120

SPICLK period

250

Delay SPICLK Rising to SPIOUT

Rising

Delay SPICLK Rising to SPIOUT

Falling

Delay SPICLK Falling to SPIOUT

Rising

Delay SPICLK Falling to SPIOUT

Falling

SPIIN to SPICLK Rising Setup time

SPIIN to SPICLK Rising Hold time

SPIIN to SPICLK Falling Setup time

SPIIN to SPICLK Falling Hold time

SPI TIMING DIAGRAMS

SPICLK

SPIOUT

SPIIN

SN00177

Figure 10. SPI Timing (PHAPOL = 1)

SPICLK

SPIOUT

SPIIN

SN00178

Figure 11. SPI Timing (PHAPOL = 0)

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

VIDEO

amb

= 0 to +70

C, V

= 3.3

0.3V, External Capacitance = 40pF

ITEM

PARAMETER

RISING/FALLING

LIMITS

UNIT

ITEM

PARAMETER

RISING/FALLING

MIN

MAX

UNIT

LOAD Pulse width

100

1600

Delay LOAD Falling to FRAME

100

3200

Delay LOAD Falling to DF

100

3200

Delay LOAD Falling to CP

100

3200

Delay CP Rising to VDAT[3:0]

VDAT to CP Rising Setup

VDAT to CP Rising Hold

NOTE:
Values shown assume a 40MHz clock for the CPU, MIN and MAX values are programmable using Video Control Registers.

VIDEO TIMING DIAGRAMS

FRAME

LOAD

VDAT[3:0]

SN00179

Figure 12. Video Timing, 4 Bit Non-Split LCD

VDAT[3:0]

SN00180

Figure 13. Video Data Timing, 4 Bit Split LCD and 8 Bit Non-Split LCD

Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseiden embedded processor

1996 Sep 24

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

DEFINITIONS

Data Sheet Identification

Product Status

Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation

Philips

Semiconductors

Р­Р»РµРєС‚СЂРѕРЅРЅС‹Р№ РєРѕРјРїРѕРЅРµРЅС‚: PR31500

РР»РµРєС‚СЂРѕРЅРЅС‹Р№ РєРѕРјРїРѕРЅРµРЅС‚: PR31500