Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

FEATURES

2-to-1 bi-directional master selector

C interface logic; compatible with SMBus standards

PCA9541/01 powers-up with Channel 0 selected

PCA9541/02 powers-up with Channel 0 selected after STOP
condition detected (bus idle) on Channel 0

PCA9541/03 powers-up with no channel selected and either
master can take control of the bus

Active LOW Interrupt Input

2 Active LOW Interrupt Outputs

Active LOW Reset Input

4 address pins allowing up to 16 devices on the I

C-bus

Channel selection via I

C-bus

Bus initialization/recovery function

Bus traffic sensor

Low Rds

switches

Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses

No glitch on power-up

Supports hot insertion

Software identical for both masters

Low stand-by current

Operating power supply voltage range of 2.3 V to 5.5 V

6.0 V tolerant Inputs

0 to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA

Packages offered: SO16, TSSOP16, HVQFN16

APPLICATIONS

High reliability systems with dual masters

Gatekeeper multiplexer on long single bus

Bus initialization/recovery for slave devices without hardware
reset

Allows masters without arbitration logic to share resources

DESCRIPTION

The PCA9541 is a 2-to-1 I

C master selector designed for high

reliability dual master I

C applications where system operation is

required, even when one master fails or the controller card is
removed for maintenance. The two masters (e.g., primary and
back-up) are located on separate I

C-buses that connect to the

same downstream I

C-bus slave devices. I

C commands are sent

by either I

C-bus master and are used to select one master at a

time. Either master at any time can gain control of the slave devices
if the other master is disabled or removed from the system. The
failed master is isolated from the system and will not affect
communication between the on-line master and the slave devices on
the downstream I

C-bus.

Three versions are offered for different architectures. PCA9541/01
with channel 0 selected at start-up, PCA9541/02 with channel 0
selected after start-up and after stop condition is detected, and
PCA9541/03 with no channel selected after start-up.

The interrupt outputs are used to provide an indication of which
master has control of the bus. One interrupt input (INT_IN) collects
downstream information and propagates it to the 2 upstream
I

C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used

to let the previous bus master know that it is not in control of the bus
anymore and to indicate the completion of the bus
recovery/initialization sequence. Those interrupts can be disabled
and will not generate an interrupt if the masking option is set.

A bus recovery/initialization if enabled sends nine clock pulses, a
not acknowledge, and a stop condition in order to set the
downstream I

C-bus devices to an initialized state before actually

switching the channel to the selected master.

An interrupt is sent to the upstream channel when the
recovery/initialization procedure is completed.

An internal bus sensor senses the downstream I

C traffic and

generates an interrupt if a channel switch occurs during a non-idle
bus condition. This function is enabled when the PCA9541
recovery/initialization is not used. The interrupt signal informs the
master that an external I

C-bus recovery/initialization needs to be

performed. It can be disabled and an interrupt will not be generated.

The pass gates of the switches are constructed such that the V

pin can be used to limit the maximum high voltage, which will be
passed by the PCA9541. This allows the use of different bus
voltages on each pair, so that 1.8 V 2.5 V or 3.3 V devices can
communicate with 5 V devices without any additional protection.

The PCA9541 does not isolate the capacitive loading on either side
of the device so the designer must take into account all trace and
device capacitances on both sides of the device, and pull-up
resistors must be used on all channels.

External pull-up resistors pull the bus to the desired voltage level for
each channel. All I/O pins are 6.0 V tolerant.

An active-LOW Reset Input allows the PCA9541 to be initialized.
Pulling the RESET pin LOW resets the I

C state machine and

configures the device to its default state as does the internal power
on reset function.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

16-Pin Plastic SO

40 to +85

PCA9541D/01

SOT109-1

16-Pin Plastic TSSOP

40 to +85

PCA9541PW/01

9541/01

SOT403-1

16-Pin Plastic HVQFN

40 to +85

PCA9541BS/01

41/1

SOT629-1

16-Pin Plastic SO

40 to +85

PCA9541D/02

SOT109-1

16-Pin Plastic TSSOP

40 to +85

PCA9541PW/02

9541/02

SOT403-1

16-Pin Plastic HVQFN

40 to +85

PCA9541BS/02

41/2

SOT629-1

16-Pin Plastic SO

40 to +85

PCA9541D/03

SOT109-1

16-Pin Plastic TSSOP

40 to +85

PCA9541PW/03

9541/03

SOT403-1

16-Pin Plastic HVQFN

40 to +85

PCA9541BS/03

41/3

SOT629-1

Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.

PIN CONFIGURATION

INT0

SDA_MST0

SCL_MST0

RESET

SCL_MST1

SDA_MST1

INT1

INT_IN

SDA_SLAVE

SCL_SLAVE

SW02008

Figure 1. SO16/TSSOP16 pin configuration.

SW02034

TOP VIEW

SCL_MST0

RESET

SCL_SLAVE

SDA_SLAVE

INT1

INT0

SDA_MST0

SCL_MST1

SDA_MST1

INT_IN

Figure 2. HVQFN16 pin configuration.

PIN DESCRIPTION

SO/TSSOP

PIN NUMBER

HVQFN PIN NUMBER

SYMBOL

FUNCTION

INT0

Active LOW interrupt output 0 (external pull-up required)

SDA_MST0

Serial data master 0 (external pull-up required)

SCL_MST0

Serial clock master 0 (external pull-up required)

RESET

Active LOW reset input (external pull-up required)

SCL_MST1

Serial clock master 1 (external pull-up required)

SDA_MST1

Serial data master 1 (external pull-up required)

INT1

Active LOW interrupt output 1 (external pull-up required)

Supply ground

Address input 0 (externally held to GND or V

)

Address input 1 (externally held to GND or V

)

Address input 2 (externally held to GND or V

)

Address input 3 (externally held to GND or V

)

SCL_SLAVE

Serial clock slave (external pull-up required)

SDA_SLAVE

Serial data slave (external pull-up required)

INT_IN

Active LOW interrupt input (external pull-up required)

Supply voltage

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

DEVICE ADDRESS

Following a START condition, the upstream master that wants to
control the I

C-bus or make a status check must send the address

of the slave it is accessing. The slave address of the PCA9541 is
shown in Figure 4. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable pins and they must be
pulled HIGH or LOW.

A1 A0

A3 A2

SW02011

R/W

FIXED

HARDWARE

SELECTABLE

Figure 4. Slave address

The last bit of the slave address defines the operation to be
performed. When set to logic 1 a read is selected while logic 0
selects a write operation.

COMMAND CODE

Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9541, which will be stored
in the Command Code register.

SW02302

NUMBER

AUTO

INCREMENT

Figure 5. Command Code

The 2 LSBS are used as a pointer to determine which register will
be accessed.

If the auto-increment flag is set (AI=1), the two least significant bits
of the Command Code are automatically incremented after a byte
has been read or written. This allows the user to program the
registers sequentially or to read them sequentially.

During a Read operation, the contents of these bits will rollover

to "00" after the last allowed register is accessed ("10").

During a Write operation, the PCA9541 will acknowledge bytes

sent to the IE and CONTROL registers but will not acknowledge
a byte sent to the Interrupt Status Register since it is a
read-only register. The 2 LSB's of the Command Code do not
roll over to 00 but stays at 10.

Only the 2 least significant bits are affected by the AI flag.

Unused bits must be programmed with zeroes. Any command code
(Write operation) different from "000AI0000", "000AI0001", and
"000AI0010" will not be acknowledged. At power-up, this register
defaults to all zeros.

Table 1.

Command Code Register

REGISTER

NAME

TYPE

Read/Write

Interrupt

Enable

CONTROL

Read/Write

Control Switch

ISTAT

Read

Interrupt

Status

NOT ALLOWED

Each system master controls its own set of registers, however they
can also read specific bits from the other system master.

PCA9541 INTERNAL REGISTER MAP

CONTROL

ISTAT

CONTROL

ISTAT

REG#00

REG#01

REG#10

REG#00

REG#01

REG#10

IE 0

CONTROL 0

ISTAT 0

MASTER 0

SCL_MST0

SDA_MST0

MASTER 1

SCL_MST1

SDA_MST1

SW02072

IE 1

CONTROL 1

ISTAT 1

PCA9541

CONTROL REGISTER DETAIL

CONTROL 0

CONTROL 1

Figure 6. Internal register map

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

INTERRUPT ENABLE AND CONTROL REGISTERS
DESCRIPTION

When a master seeks control of the bus by connecting its I

channel to the PCA9541 downstream channel, it has to write to the
Control Register (Reg#01)

Bits MYBUS and BUSON allow the master to take control of the
bus.

The MYBUS and the NMYBUS bits determine which master has
control of the bus. Tables 4 and 5 explain which master gets control
of the bus and how. There is no arbitration. Any master can take
control of the bus when it wants regardless of whether the other
master is using it or not.

The BUSON and the NBUSON bits determine whether the upstream
bus is connected or disconnected to/from the downstream bus.

Internally, the state machine does the following:

If the combination of the BUSON and the NBUSON bits causes

the upstream to be disconnected from the downstream bus,
then that is done. So in this case, the values of the MYBUS and
the NMYBUS do not matter.

If a master was connected to the downstream bus prior to the

disconnect, then an interrupt is sent on the respective interrupt
output in an attempt to let that master know that it is no longer
connected to the downstream bus. This is indicated by setting
the BUSLOST bit in the Interrupt Status Register.

If the combination of the BUSON and the NBUSON bits causes

a master to be connected to the downstream bus and if there is
no change in the BUSON bits since when the disconnect took
effect, then the master requesting the bus is connected to the
downstream bus. If it requests a bus initialization sequence,
then it is performed.

If there is no change in the combination of the BUSON and the

NBUSON bits and a new master wants the bus, then the
downstream bus is disconnected from the old master that was
using it and the new master gets control of it. Again, the bus
initialization if requested is done. The appropriate interrupt
signals are generated.

After a master has sent the bus control request:
1. The previous master is disconnected from the I

C-bus. An

interrupt to the previous master is sent through its INT line to let
it know that it lost control of the bus. BUSLOST bit in the
Interrupt Status Register is set. This interrupt can be masked by
setting the BUSLOSTMSK bit to 1.

2. A built-in bus initialization/recovery function can take temporary

control of the downstream channel to initialize the bus before
making the actual switch to the new bus master. This function is
activated by setting the BUSINIT to 1 by the master during the
same write sequence as the one programming MYBUS and
BUSON bits.

When activated and whether the bus was previously idle or not:

9 clock pulses are sent on the SCL_SLAVE.

SDA_SLAVE line is released (HIGH) when the clock pulses are

sent to SCL_SLAVE. This is equivalent to sending 8 data bits
and a not acknowledge

Finally a STOP condition is sent to the downstream slave

channel.

This sequence will complete any read transaction which was
previously in process and the downstream slave configured as a
slave-transmitter should release the SDA line because the
PCA9541 did not acknowledge the last byte.

3. When the initialization has been requested and completed, the

PCA9541 sends an interrupt to the new master through its INT
line and connects the new master to the downstream channel.
BUSINIT bit in the Interrupt Status Register is set. The switch
operation occurs after the master asking the bus control
has sent a STOP command. This interrupt can be masked by
setting the BUSINITMSK bit to 1.

4. When the bus initialization/recovery function has not been

requested (BUSINIT=0), the PCA9541 connects the new master
to the slave downstream channel. The switch operation occurs
after the master asking the bus control has sent a STOP
command. PCA9541 sends an interrupt to the new master
through its INT line if the built-in bus sensor function detects a
non-idle condition in the downstream slave channel at the
switching time. BUSOK bit in the Interrupt Status Register is set.
This means that a STOP condition has not been detected in the
previous bus communication and that an external bus
recovery/initialization must be performed. If an idle condition has
been detected at the switching time, no interrupt will be sent.
This interrupt can be masked by setting the BUSOKMSK bit to 1.

Interrupt status can be read. See paragraph INTERRUPT STATUS
REGISTER DESCRIPTION for more information.

The MYTEST and the NMYTEST bits cause the interrupt pins of the
respective masters to be activated for a "functional interrupt test".

NOTES:
1. The regular way to proceed is that a master asks to take the

control of the bus by programming MYBUS and BUSON bits.
Nevertheless, the same master can also decide to give up the
control of the bus and give it to the other master. This is also
done by programming the MYBUS and BUSON bits.

2. Any writes either to the Interrupt Enable Register or the Control

Register cause the respective register to be updated on the 9th
clock cycle, i.e. on the rising edge of the acknowledge clock
cycle.

3. The actual switch from one channel to another or the switching

off of both the channels happens on a STOP command.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

Register 0: Interrupt Enable (IE) Register (B1B0 = 00)

This register allows a master to read and/or write (if needed) Mask options for its own channel.

The Interrupt Enable Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Interrupt Enable
Registers, one for each upstream channel.

When Master 0 reads/writes in this register, the internal Interrupt Enable Register 0 will be accessed.

When Master 1 reads/writes in this register, the internal Interrupt Enable Register 1 will be accessed.

BIT

SYMBOL

BUSLOSTMSK

BUSOKMSK

BUSINITMSK

INTINMSK

Table 2.

Register 0

BIT

SYMBOL

READ/

WRITE

DEFAULT

DESCRIPTION

INTINMSK

R/W

0: Interrupt on INT_IN will generate an interrupt on INT

INTINMSK

R/W

1: Interrupt on INT_IN will not generate an interrupt on INT (masked)

BUSINITMSK

R/W

0: After connection is requested and Bus Initialization requested (BUSINIT = 1), an

interrupt on INT will be generated when the bus initialization is done.
Note: Channel switching is done after bus initialization completed.

BUSINITMSK

R/W

1: After connection is requested and Bus Initialization requested (BUSINIT = 1), an

interrupt on INT will not be generated when the bus initialization is done (masked).
Note: Channel switching is done after bus initialization completed.

BUSOKMSK

R/W

0: After connection is requested and Bus Initialization not requested (BUSINIT = 0), an

interrupt on INT will be generated when a non-Idle situation has been detected on the
downstream slave channel by the bus sensor at the switching moment.
Note: Channel switching is done automatically after the STOP command.

BUSOKMSK

R/W

1: After connection is requested and Bus Initialization not requested (BUSINIT = 0), an

interrupt on INT will not be generated when a non-Idle situation has been detected on
the downstream slave channel by the bus sensor at the switching moment (masked).
Note: Channel switching is done automatically after the STOP command.

BUSLOSTMSK

R/W

0: An interrupt on INT will be generated after the other master has been been

disconnected

BUSLOSTMSK

R/W

1: An interrupt on INT will not be generated after the other master has been been

disconnected.

NOT USED

R only

NOT USED

R only

NOT USED

R only

NOT USED

R only

NOTE:
Default values are the same for PCA9541/01, PCA9541/02, and PCA9541/03

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

Register 1: Control Register (B1B0 = 01)

x stands for 0 or 1 and is applied to the master that reads or writes in the Control Register explained below

The Control Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Control Registers, one for
each upstream channel.

When master 0 reads/writes in this register, the internal Control Register 0 will be accessed.

When master 1 reads/writes in this register, the internal Control Register 1 will be accessed.

BIT

SYMBOL

NTESTON

TESTON

BUSINIT

NBUSON

BUSON

NMYBUS

MYBUS

Table 3.

Register 1

BIT

SYMBOL

READ/

WRITE

DEFAULT

DESCRIPTION

MYBUS

R/W

See

Table 6

MYBUS bit along with the NMYBUS bit decides which upstream channel is connected
to the downstream channel

See Table 4

NMYBUS

R only

See

NMYBUS bit is a copy of the MYBUS bit for the other channel

NMYBUS

R only

Table 6

See Table 4

BUSON

R/W

See

BUSON bit along with the NBUSON bit decides whether any upstream channel is
connected to the downstream channel or not

BUSON

R/W

Table 6

connected to the downstream channel or not

See Table 5

NBUSON

R only

See

NBUSON bit is a copy of the BUSON bit for the other channel

NBUSON

R only

Table 6

See Table 5

BUSINIT

R/W

0: Bus initialization not requested

BUSINIT

R/W

1 : Bus initialization requested

NOT USED

R only

TESTON

R/W

0: a Logic Level High to the INT line is sent (interrupt cleared)

TESTON

R/W

1: a Logic Level Low to the INT line is sent (interrupt generated)

NTESTON

R only

0: a Logic Level High to the INT line of the other channel is sent (interrupt cleared)

NTESTON

R only

1: a Logic Level Low to the INT line of the other channel is sent (interrupt generated)

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

Table 4.

MYBUS and NMYBUS Truth Table

NMYBUS

MYBUS

SLAVE CHANNEL

to the switching initiator

to the other channel

to the switching initiator

Table 5.

BUSON and NBUSON Truth Table

NBUSON

BUSON

SLAVE CHANNEL

OFF

NOTES:
1. Switch to the new channel is done when the master initiating the switch request sends a STOP command to the PCA9541.

2. If Master 0 wants to change the connection to the downstream channel in any way, it needs to write to its Control Register (Reg#01), and

then send a STOP command because an update of the connection to the downstream according to the values in the two internal Control
Registers happens only on a STOP command. Writing to one control register followed by a STOP condition on the other Master's channel
will not cause an update to the downstream connection.

3. When both masters request a switch to their own channel at the same time, the master who last wrote to its control register before the

PCA9541 receives a STOP command wins the switching sequence. There is no arbitration performed.

4. Auto Increment feature (AI=1) allows to program the PCA9541 in 4 bytes:

Start

111A3A2A1A0 + 0

PCA9541 Address + Write

00010000

Select Reg#00 with AI = 1

Data Reg#00

Interrupt Enable Register Data

Data Reg#01

Control Register Data

Stop

Table 6.

Default Control Register Values

BIT

VERSION

SYMBOL

NTESTON

TESTON

NOT

USED

BUSINIT

NBUSON

BUSON

NMYBUS

MYBUS

PCA9541/01

MST_0

PCA9541/01

MST_1

PCA9541/02

MST_0

PCA9541/02

MST_1

PCA9541/03

MST_0

PCA9541/03

MST_1

PCA9541/02

MST_0

(AFTER STOP)

MST_1

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

Table 7 describes which command needs to be written to the Control
Register when a master device wants to take control of the I

C-bus.

Byte written to the Control Register is a function of the current
I

C-bus control status performed after an initial reading of the

Control Register.

Current status of the I

C-bus is determined by the bits MYBUS,

NMYBUS, BUSON and NBUSON is one of the following:

The master reading its Control Register does not have control and

the I

C-bus is off.

The master reading its Control Register does not have control and

the I

C-bus is on.

The master reading its Control Register has control and the

C-bus is off.

The master reading its Control Register has control and the

C-bus is on.

C-bus off' means that upstream and downstream channels are not

connected together.

C-bus on' means that upstream and downstream channels are

connected together.

Remark:

Only the 4 LSBs of the Control Register are described in

Table 7 since only those bits control the I

C-bus control. The logic

value for the 4 MSBs is specific to the application and are not
discussed in the table.

The Read sequence is performed by the master as following:
S -- 111xxxx0 -- 000x0001 -- Sr -- 111xxxx1 -- DataRead -- P

The Write sequence is performed by the master as following:
S -- 111xxxx0 -- 000x0001 -- DataWritten -- P

Table 7.

Bus control sequence

Read Control Register performed by the Master

Write Control Register performed by the Master

Byte Read

only the

4 LSBs

are shown

Status

NBUSON

BUSON

NMYBUS

MYBUS

Byte Written

only the 4 LSBs are shown

(see Note 1)

Action performed

to take Mastership

Hex

Binary

Hex

0x0

Bus off

Has control

x1x0

0x4

Bus on

0x1

Bus off

No control

x1x0

0x4

Bus on, Take control

0x2

Bus off

No control

x1x1

0x5

Bus on, Take control

0x3

Bus off

Has control

x1x1

0x5

Bus on

0x4

Bus on

Has control

No write required

No change

0x5

Bus on

No control

x1x0

0x4

Take control

0x6

Bus on

No control

x1x1

0x5

Take control

0x7

Bus on

Has control

No write required

No change

0x8

Bus on

Has control

No write required

No change

0x9

Bus on

No control

x0x0

0x0

Take control

0xA

Bus on

No control

x0x1

0x1

Take control

0xB

Bus on

Has control

No write required

No change

0xC

Bus off

Has control

x0x0

0x0

Bus on

0xD

Bus off

No control

x0x0

0x0

Bus on, Take control

0xE

Bus off

No control

x0x1

0x1

Bus on, Take control

0xF

Bus off

Has control

x0x1

0x1

Bus on

NOTES:
1. x0x0 = 0x0, 0x2, 0x8, 0xA

x0x1 = 0x1, 0x3, 0x9, 0xB
x1x0 = 0x4, 0x6, 0xC, 0xE
x1x1 = 0x5, 0x7, 0xD, 0xF

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

INTERRUPT STATUS REGISTERS DESCRIPTION

The PCA9541 provides 4 different types of interrupt:
1. To indicate to the former I

C-bus master that it is not in control of

the bus anymore.

2. To indicate to the new I

C-bus master that:

The bus recovery/initialization has been performed and that

the downstream channel connection has been done (built-in
bus recovery/initialization active).

A "bus not well initialized" condition has been detected by the

PCA9541 when the switch has been done (built-in bus
recovery/initialization not active). This information can be
used by the new master to initiate its own bus
recovery/initialization sequence.

3. Indicate to both I

C upstream masters that a downstream

interrupt has been generated through the INT_IN pin.

4. Functionality wiring test.

Bus control lost interrupt

When an upstream master takes control of the I

C-bus while the

other channel was using the downstream channel, an interrupt is
generated to the master losing control of the bus (INT line goes
LOW to let the master know that it lost the control of the bus)
immediately after disconnection from the downstream channel.

By setting the BUSLOSTMSK bit to 1, the interrupt is masked and
the upstream master that lost the I

C-bus control does not receive

an interrupt (INT line does not go LOW).

Recovery/initialization interrupt

Before switching to a new upstream channel, an automatic bus
recovery/initialization can be performed by the PCA9541. This
function is requested by setting the BUSINIT bit to 1. When the
downstream bus has been initialized, an interrupt to the new master
is generated (INT line goes LOW).

By setting the BUSINITMSK bit to 1, the interrupt is masked and the
new master does not receive an interrupt (INT line does not go
LOW).

When the automatic bus recovery/initialization is not requested, if
the built-in bus sensor function (sensing permanently the

downstream I

C traffic) detects a non-idle condition (previous bus

channel connected to the downstream slave channel, was between
a START and STOP condition), then an interrupt to the new master
is sent (INT line goes LOW). This interrupt tells the new master that
an external bus recovery/initialization must be performed. By setting
the BUSOKMSK bit to 1, the interrupt is masked and the new
master does not receive an interrupt (INT line does not go LOW).

NOTE: In this particular situation, after the switch to the new master
is performed, a read of the Interrupt Status Register is not
possible if the switch happened in the middle of a read
sequence because the new master does not have control of the
SDA line

Downstream interrupt

An interrupt can also be generated by a downstream device by
asserting the INT_IN pin LOW. When INT_IN is asserted LOW and if
both INTINMSK bits are not set to 1 by either master, INT0 and INT1
both go LOW.

By setting the INTINMSK bit to 1 by a master and/or the INTINMSK
bit to 1 by the other master, the interrupt(s) is (are) masked and the
corresponding masked channel(s) does (do) not receive an interrupt
(INT0 and/or INT1 line does (do) not go LOW).

Functional test interrupt

A master can send an interrupt to itself to test its own INT wire or
send an interrupt to the other master to test its INT line. This is done
by:

Setting the TESTON bit to 1 to test its own INT line.

Setting the NTESTON bit to 1 to test the other master INT

line.

Setting the TESTON and/or NTESTON bits to 0 by a master will
clear the interrupt(s).

NOTE: Interrupt outputs have an open-drain structure. Interrupt
input does not have any internal pull-up resistor and must not be left
floating (e.g., pulled high to V

through resistor) in order to avoid

any undesired interrupt conditions.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

Register 2: Interrupt Status Register (B1B0 = 10)

The Interrupt Status Register for both the masters is identical and is described below. Nevertheless, there are physically 2 internal Interrupt
Registers, one for each upstream channel.

When Master 0 reads this register, the internal Interrupt Register 0 will be accessed.

When Master 1 reads this register, the internal Interrupt Register 1 will be accessed.

BIT

SYMBOL

NMYTEST

MYTEST

BUSLOST

BUSOK

BUSINIT

INTIN

Table 8.

Register 2

BIT

SYMBOL

READ/

WRITE

DEFAULT

DESCRIPTION

INTIN

R only

0: No interrupt on interrupt input (INT_IN)

INTIN

R only

1: Interrupt on interrupt input (INT_IN)

0: No interrupt generated by the bus recovery/initialization function

BUSINIT

R only

1: Interrupt generated by the bus recovery/initialization function

recovery/initialization done

0: No interrupt generated by bus sensor function

BUSOK

R only

1: Interrupt generated by bus sensor function (masked when bus

recovery/initialization requested) Bus was not idle when the switch
occurred

BUSLOST

R only

0: No interrupt generated to the previous master when switching to the new

one is initiated

BUSLOST

R only

1: Interrupt generated to the previous master when switching to the new

one is initiated

NOT USED

R only

NOT USED

R only

MYTEST

R only

0: No interrupt generated by TESTON bit f (TESTON = 0)

MYTEST

R only

1: Interrupt generated by TESTON bit (TESTON = 1)

NMYTEST

R only

0: No interrupt generated due to NTESTON bit from the other master

(NTESTON = 0 from the other master)

NMYTEST

R only

1: Interrupt generated due to TESTON bit from the other master

(NTESTON = 1 from the other master)

NOTES:
1. Interrupt on a master is cleared after TESTON bit is cleared the same master or NTESTON bit is cleared by the other master.

2. If the interrupt condition remains on INT_IN after the Read sequence, another interrupt will be generated (if the interrupt has not been

masked)

3. Default values are the same for PCA9541/01, PCA9541/02 and PCA9541/03

4. Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:

INT_IN lines goes HIGH for INTIN bit

TESTON bit is cleared for MYTEST bit

NTESTON bit is cleared for NMYTEST bit

5. BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register gets cleared after a Read of the same register is done. Precisely, the

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

POWER-ON RESET

When power is applied to V

, an internal Power-On Reset holds

the PCA9541 in a reset condition until V

has reached V

POR

. At

this point, the reset condition is released and the internal registers
are initialized to their default states, with:

Default

Stop Detect

PCA9541/01

Channel 0

PCA9541/02

Channel 0

PCA9541/03

No Channel

1. PCA9541/01: after power-up and/or insertion of the device in the

main I

C-bus, the upstream Channel 0 and the downstream

slave channel are connected together.

2. PCA9541/02: after power-up and/or insertion of the device in the

main I

C-bus, the upstream Channel 0 and the downstream

slave channel are connected together after a STOP condition
has been detected by the PCA9541/02 on Channel 0.

If the bus was not idle, Channel 0 and the downstream slave

device will be connected together as soon as a STOP
condition occurs at the conclusion of the transmission
sequence on Channel 0.

If the bus was idle, then Channel 0 is connected to the

downstream slave channel after a STOP condition is detected
on Channel 0. This I

C-bus command may or may not be

addressed to the PCA9541/02.

If a switch to channel 1 (initiated by the master on channel 1)

is requested (before or after the default switch to Channel 0
has been performed), the upstream channel 1 is connected to
the downstream slave channel when the master located in
Channel 1 sends the STOP command.

3. PCA9541/03: after power-up and/or insertion of the device in the

main I

C-bus, no channel will be connected to the downstream

channel. The device is ready to receive a START condition and
its address by a master.

If either register writes to its Control Register, then the
connection between the upstream and the downstream channels
is determined by the values on the Control Registers.

Thereafter, V

must be lowered below 0.2 V to reset the device.

EXTERNAL RESET

A reset can be accomplished by holding the RESET pin LOW for a
minimum of t

. The PCA9541 registers and I

C state machine will

be held in their default states until the RESET input is once again
HIGH. This input typically requires a pull-up resistor to V

Default states are:

C upstream Channel 0 connected to the I

C downstream

channel for the PCA9541/01

no I

C upstream channel connected to the I

C downstream

channel for the PCA9541/02 with Channel 0 connected to the
downstream I

C channel after detection of a STOP on the

upstream channel.

no I

C upstream channel connected to the I

C downstream

channel for the PCA9541/03.

VOLTAGE TRANSLATION

The pass gate transistors of the PCA9541 are constructed such that
the V

voltage can be used to limit the maximum voltage that will

be passed from one I

C-bus to another.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

pass

vs. V

2.5

3.0

3.5

4.0

4.5

5.0

5.5

pass

MINIMUM

TYPICAL

MAXIMUM

SW00820

2.0

Figure 7. V

pass

voltage

Figure 7 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9541 to act as a voltage translator, the V

pass

voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main buses were running at 5 V, and the
downstream bus was 3.3 V, then V

pass

should be equal to or below

3.3 V to effectively clamp the downstream bus voltages. Looking at
Figure 7, we see that V

pass

(max.) will be at 3.3 V when the

PCA9541 supply voltage is 3.5 V or lower so the PCA9541 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 16).

More Information on voltage translation can be found in Application
Note AN262

PCA954X family of I

C/SMBus multiplexers and

switches.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

CHARACTERISTICS OF THE I

C-BUS

The I

C-bus is for 2-way, 2-line communication between different ICs

or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see FIgure 8).

SDA

SCL

SW00363

data line

stable;

data valid

change

of data

allowed

Figure 8. Bit transfer

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 9).

System configuration

A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 10).

SDA

SCL

SW00365

SDA

SCL

START condition

STOP condition

Figure 9. Definition of start and stop conditions

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

SW00366

MULTIPLEXER

SLAVE

Figure 10. System configuration

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C master selector with interrupt logic and reset

2004 Oct 01

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

SW00368

DATA OUTPUT

BY RECEIVER

START condition

clock pulse for
acknowledgement

acknowledge

not acknowledge

Figure 11. Acknowledgement on the I

C-bus

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I C master selector with interrupt logic and reset

2004 Oct 01

SLAVE ADDRESS

start condition

R/W

SW02306

COMMAND CODE REGISTER

DATA MASK REGISTER

DATA CONTROL REGISTER

Stop condition

acknowledge

from slave

acknowledge
from slave

Auto
increment

acknowledge
from slave

Figure 12. Write to the Mask and Control Registers using the Auto-Increment (AI) bit

NOTE: If a 3rd data byte is sent, it will not be acknowledged by the PCA9541.

A3 A2

SLAVE ADDRESS

start condition

R/W

acknowledge
from slave

COMMAND CODE

ACCESS TO REGISTER

XX = 00, 01, OR 10

SW02307

stop

condition

acknowledge
from slave

no acknowledge-

from master

A3 A2

A3 A2 A1

R/W

SLAVE ADDRESS

re-start
condition

Auto

Increment

acknowledge
from master

XX = 00 : INTERRUPT ENABLE REGISTER

CONTROL REGISTER

INT REGISTER

XX = 01 : CONTROL REGISTER

INT REGISTER

INTERRUPT ENABLE REGISTER

XX = 10 : INT REGISTER

INTERRUPT ENABLE REGISTER

CONTROL REGISTER

Figure 13. Read the 3 registers using the Auto-Increment (AI) bit

NOTE: If a 4th data byte is read, the first Register will be accessed.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I C master selector with interrupt logic and reset

2004 Oct 01

A3 A2

SLAVE ADDRESS

start condition

R/W

acknowledge
from slave

COMMAND CODE REGISTER

SW02308

stop condition

acknowledge
from slave

Auto

Increment

DATA CONTROL REGISTER

BUSINIT

SDA_MST0

SCL_MST0

INT1

SDA_SLAVE

SCL_SLAVE

INT0

AFTER THE STOP CONDITION,
MASTER 1 IS DISCONNECTED
FROM THE DOWNSTREAM
CHANNEL

IF THE INTERRUPT IS NOT MASKED

(BUSLOSTMSK = 0)

IF THE INTERRUPT IS NOT MASKED

(BUSINITMSK = 0)

MASTER 1 HAS CONTROL OF THE BUS

PCA9541 HAS CONTROL OF THE BUS

MASTER 0 HAS

CONTROL OF

THE BUS

MASTER 0 MUST WAIT FOR THE "BUS FREE

TIME" VALUE (BETWEEN STOP AND START)

DEFINED IN THE I

C SPECIFICATION

BEFORE SENDING COMMANDS TO

THE DOWNSTREAM DEVICES

BUSON

MYBUS

Figure 14. Write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization requested)

NOTE: We assume that a Read of the control register was done by Master 1 and that 000x1010 was read.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I C master selector with interrupt logic and reset

2004 Oct 01

SLAVE ADDRESS

start condition

R/W

acknowledge
from slave

COMMAND CODE REGISTER

SW02309

stop condition

acknowledge
from slave

Auto

Increment

DATA CONTROL REGISTER

SDA_MST0

SCL_MST0

INT1

INT0

AFTER THE STOP CONDITION, MASTER 1 IS
DISCONNECTED FROM THE DOWNSTREAM
CHANNEL AND MASTER 0 IS CONNECTED
TO THE DOWNSTREAM CHANNEL

IF THE INTERRUPT IS NOT MASKED

(BUSLOSTMSK = 0)

IF MASTER 1 WAS NOT IDLE AT THE SWITCHING MOMENT

AND THE INTERRUPT IS NOT MASKED

(BUSOKMSK = 0)

MASTER 1 HAS CONTROL OF THE BUS

MASTER 0 HAS CONTROL OF THE BUS

MASTER 0 MUST WAIT FOR THE "BUS FREE
TIME" VALUE (BETWEEN STOP AND START)
DEFINED IN THE I

C SPECIFICATION

BEFORE SENDING COMMANDS TO
THE DOWNSTREAM DEVICES

Figure 15. Write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization not requested)

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C demultiplexer with interrupt logic and reset

2004 Oct 01

TYPICAL APPLICATION

PCA9541

SD1

SC1

SDA_MST0

SCL_MST0

RESET

3.3 V

MASTER 0

SW02010

SDA0

SCL0

INT0

INT_IN

3.3 V

MASTER 1

RESET0

INT0

SDA1

SCL1

RESET1

INT1

SDA_MST1

SCL_MST1

INT1

SLAVE 2

SLAVE 1

SLAVE 3

INT

SDA

SCL

SDA

SCL

SDA

SCL

SLAVE CARD

Figure 16. Typical application

SPECIFIC APPLICATIONS

The PCA9541 is a 2-to-1 I

C master selector designed for dual

master, high reliability I

C applications, where continuous

maintenance and control monitoring is required even if one master
fails or its controller card is removed for maintenance. The PCA9541
can also be used in other applications, such as where masters
share the same resource but cannot share the same bus, as a
gatekeeper multiplexer in long single bus applications or as a bus
initialization/recovery device.

HIGH RELIABILITY SYSTEMS

In a typical multi-point application, shown in Figure 17, the two
masters (e.g., primary and back-up) are located on separate
I

C-buses that connect to multiple downstream I

C-bus slave

cards/devices via a PCA9541/01 for non-hot swap applications or
the PCA9541/02 for hot swap applications to provide high reliability
of the I

C-bus.

SR02462

SCL0

SDA0

SCL1

SDA1

MASTER 1

MASTER 0

PCA9541

Figure 17. High Reliability Backplane Application

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C demultiplexer with interrupt logic and reset

2004 Oct 01

C commands are sent via the primary or back-up master and

either master can take command of the I

C-bus. Either master at

any time can gain control of the slave devices if the other master is
disabled or removed from the system. The failed master is isolated
from the system and will not affect communication between the
on-line master and the slave devices located on the cards.

For even higher reliability in multi-point backplane applications,
two dedicated masters can be used for every card as shown in
Figure 18.

SR02463

SCL0

SDA0

SCL1

SDA1

MASTER 1

MASTER 0

PCA9541

SCL0

SDA0

SCL1

SDA1

MASTER 1

MASTER 0

PCA9541

SCL0

SDA0

SCL1

SDA1

MASTER 1

MASTER 0

PCA9541

SCL0

SDA0

SCL1

SDA1

MASTER 1

MASTER 0

PCA9541

Figure 18. Very High Reliability Backplane Application

MASTERS WITH SHARED RESOURCES

Some masters may not be multi-master capable or some masters
may not work well together and continually lock up the bus. The
PCA9541 can be used to separate the masters, as shown in
Figure 19, but still allow shared access to slave devices, such as
Field Replaceable Unit (FRU) EEPROMs or temperature sensors.

PCA9541

SLAVE A0

SLAVE A1

SLAVE A2

MASTER A

PCA9541

SLAVE B0

SLAVE B1

SLAVE B2

MASTER B

MAIN

MASTER

SW02101

ASSEMBLY A

ASSEMBLY B

SDA/SCL

Figure 19. Masters with Shared Resources Application

GATEKEEPER MULTIPLEXER

The PCA9541/03 can act as a gatekeeper multiplexer in applications
where there are multiple I

C devices with the same fixed address

(e.g., EEPROMs with address of "Z" as shown in Figure 20)
connected in a multi-point arrangement to the same I

C-bus. Up to

16 hot swappable cards/devices can be multiplexed to the same bus
master by using one PCA9541/03 per card/device. Since each
PCA9541/03 has its own unique address (e.g., "A", "B", "C", etc), the
EEPROMs can be connected to the master, one at a time, by
connecting one PCA9541/03 (Master 0 position) while keeping the
rest of the cards/devices isolated (off position).

The alternative, shown with dashed lines, is to use a PCA9548
1-to-8 channel switch on the master card and run 8 I

C-buses, one

to each EEPROM card, to multiplex the master to each card. The
number of card pins used is the same in either case, but there are 7
less pairs of SDA/SCL traces on the PC board if the PCA9541/03 is
used.

SW02099

PCA9541

MASTER 0

PCA9548

EEPROM

Figure 20. Gatekeeper Multiplexer Application

BUS INITIALIZATION/RECOVERY

If the I

C-bus is hung, I

C devices without a hardware reset pin

(e.g., Slave 1 and 2 in Figure 21) can be isolated from the master by
the PCA9541/03. The PCA9541/03 disconnects the bus when it is
reset via the hardware reset line, restoring the master's control of
the rest of the bus (e.g., Slave 0). The bus master can then
command the PCA9541/03 to send 9 clock pulses/ stop condition to
reset the downstream I

C devices before they are reconnected to

the master or leave the downstream devices isolated.

MASTER

SW02100

SLAVE 0

SLAVE 1

SLAVE 2

SDA/SCL

SDA

SCL

RESET

SLAVE

C-bus

PCA9541/03

Figure 21. Bus Initialization/Recovery Application

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C demultiplexer with interrupt logic and reset

2004 Oct 01

ABSOLUTE MAXIMUM RATINGS

1, 2

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

CONDITIONS

RATING

UNIT

DC supply voltage

0.5 to +7.0

DC input voltage

0.5 to +7.0

DC input current

DC output current

Supply current

100

Supply current

100

tot

total power dissipation

400

stg

Storage temperature range

60 to +150

amb

Operating ambient temperature

40 to +85

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150

DC CHARACTERISTICS

= 2.3 V to 3.6 V; V

= 0 V; T

amb

= 40

C to +85

C; unless otherwise specified. (See page 21 for V

= 3.6 V to 5.5 V)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply

Supply voltage

2.3

3.6

Supply current

Operating mode; V

= 3.6 V; no load;

= V

or V

; f

SCL

= 100 kHz

152

200

stb

Standby current

Standby mode; V

= 3.6 V; no load;

= V

or V

; f

SCL

= 0 kHz

100

POR

Power-on reset voltage (Note 1)

no load; V

= V

or V

1.5

2.1

Input SCL; input/output SDA (upstream and downstream channels)

LOW-level input voltage

0.5

0.3V

HIGH-level input voltage

0.7V

LOW-level output current

= 0.4 V

LOW-level out ut current

= 0.6 V

Leakage current

= V

or V

Input capacitance

= V

Select inputs A0 to A3 / INT_IN / RESET

LOW-level input voltage

0.5

+0.3V

HIGH-level input voltage

0.7V

Input leakage current

= V

or V

Input capacitance

= V

Pass Gate

Switch resistance

= 3.0 V to 3.6 V, V

= 0.4 V, I

= 15 mA

Switch resistance

= 2.3 V to 2.7 V, V

= 0.4 V, I

= 10 mA

swin

= V

= 3.3 V; I

swout

= 100

2.2

Switch output voltage

swin

= V

= 3.0 V to 3.6 V; I

swout

= 100

1.6

2.8

Pass

Switch out ut voltage

swin

= V

= 2.5 V; I

swout

= 100

1.5

swin

= V

= 2.3 V to 2.7 V; I

swout

= 100

1.1

2.0

Leakage current

= V

or V

INT0 and INT1 outputs

LOW-level output current

= 0.4 V

NOTE:
1. V

must be lowered to 0.2 V in order to reset part.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C demultiplexer with interrupt logic and reset

2004 Oct 01

DC CHARACTERISTICS

= 3.6 V to 5.5 V; V

= 0 V; T

amb

= 40

C to +85

C; unless otherwise specified. (See page 20 for V

= 2.3 V to 3.6 V)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply

Supply voltage

3.6

5.5

Supply current

Operating mode; V

= 5.5 V;

no load; V

= V

or V

;

SCL

= 100 kHz

349

600

stb

Standby current

Standby mode; V

= 5.5 V;

no load; V

= V

or V

;

SCL

= 0 kHz

200

POR

Power-on reset voltage (Note 1)

no load; V

= V

or V

1.5

2.1

Input SCL; input/output SDA (upstream and downstream channels)

LOW-level input voltage

0.5

0.3V

HIGH-level input voltage

0.7V

LOW level output current

= 0.4 V

LOW-level output current

= 0.6 V

LOW-level input current

= V

HIGH-level input current

= V

100

Input capacitance

= V

Select inputs A0 to A3 / INT_IN / RESET

LOW-level input voltage

0.5

+0.3V

HIGH-level input voltage

0.7V

Input leakage current

= V

or V

+50

Input capacitance

= V

Pass Gate

Switch resistance

= 4.5 V to 5.5 V; V

= 0.4 V; I

= 15 mA

Switch output voltage

swin

= V

= 5.0 V; I

swout

= 100

3.6

Pass

Switch output voltage

swin

= V

= 4.5 to 5.5 V; I

swout

= 100

2.6

4.5

Leakage current

= V

or V

+100

INT0 and INT1 outputs

LOW-level output current

= 0.4 V

NOTE:
1. V

must be lowered to 0.2 V in order to reset part.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C demultiplexer with interrupt logic and reset

2004 Oct 01

AC CHARACTERISTICS

SYMBOL

PARAMETER

STANDARD-MODE

C-bus

FAST-MODE

C-bus

UNIT

MIN

MAX

MIN

MAX

Propagation delay from SDA to SD

or SCL to SC

0.3

SCL

SCL clock frequency

100

400

kHz

SCLIR

SCL bus initialization/recovery clock frequency

150

kHz

BUF

Bus free time between a STOP and START condition

4.7

1.3

HD;STA

Hold time (repeated) START condition
After this period, the first clock pulse is generated

4.0

0.6

LOW

LOW period of the SCL clock

4.7

1.3

HIGH

HIGH period of the SCL clock

4.0

0.6

SU;STA

Set-up time for a repeated START condition

4.7

0.6

SU;STO

Set-up time for STOP condition

4.0

0.6

HD;DAT

Data hold time

3.45

0.9

SU;DAT

Data set-up time

250

100

Rise time of both SDA and SCL signals

1000

20 + 0.1C

300

Fall time of both SDA and SCL signals

300

20 + 0.1C

300

Capacitive load for each bus line

400

Pulse width of spikes which must be suppressed
by the input filter

VD:DATL

Data valid (HL)

VD:DATH

Data valid (LH)

0.6

VD:ACK

Data valid Acknowledge

INT0 and INT1 outputs

INT_in to INT1 or INT2 active valid time

INT_in to IINT1 or INT2 inactive delay time

pwr

LOW level pulse width rejection or INT_in input

pwr

HIGH level pulse width rejection or INT_in input

0.5

RESET

Pulse width LOW reset

rst

Reset time (SDA clear)

500

REC:STA

Recovery to Start

5, 6

NOTES:
1. Pass gate propagation delay is calculated from the 20

typical R

and the 15 pF load capacitance.

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V

IH(min)

of the SCL signal) in order to bridge

the undefined region of the falling edge of SCL.

3. C

= total capacitance of one bus line in pF.

4. Measurements taken with 1 k

pull-up resistor and 50 pF load.

5. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
6. Upon reset, the full delay will be the sum of t

RESET

and the RC time constant of the SDA bus.

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I

C demultiplexer with interrupt logic and reset

2004 Oct 01

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2004

Date of release: 10-04

Document number:

9397 750 13629

Philips
Semiconductors

Data sheet status

[1]

Objective data sheet

Preliminary data sheet

Product data sheet

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PCA9541