LPC2104/2105/2106
Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with
64 kB/32 kB/16 kB RAM
Rev. 04 -- 05 February 2004
Product data
1.
General description
The LPC2104, 2105 and 2106 are based on a 16/32 bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, together with 128 kbytes (kB) of
embedded high speed flash memory. A 128 bit wide memory interface and a unique
accelerator architecture enable 32 bit code execution at maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb Mode reduces code by
more than 30% with minimal performance penalty.
Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip
SRAM options up to 64 kilobytes, they are very well suited for communication
gateways and protocol converters, soft modems, voice recognition and low end
imaging, providing both large buffer size and high processing power. Various 32 bit
timers, PWM channels and 32 GPIO lines make these microcontrollers particularly
suitable for industrial control and medical systems.
2.
Features
2.1 Key features
s
16/32 bit ARM7TDMI-S processor.
s
16/32/64 kB on-chip Static RAM.
s
128 kB on-chip Flash Program Memory. 128 bit wide interface/accelerator
enables high speed 60 MHz operation.
s
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot-loader software. Flash programming takes 1 ms per 512 byte line. Single
sector or full chip erase takes 400 ms.
s
Vectored Interrupt Controller with configurable priorities and vector addresses.
s
EmbeddedICE-RT interface enables breakpoints and watchpoints. Interrupt
service routines can continue to execute whilst the foreground task is debugged
with the on-chip RealMonitor software.
s
Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of
instruction execution.
s
Multiple serial interfaces including two UARTs (16C550), Fast I
2
C (400 kbits/s)
and SPI.
s
Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time
Clock and Watchdog.
s
Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48
(7
7 mm
2
) package.
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 -- 05 February 2004
2 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
s
60 MHz maximum CPU clock available from programmable on-chip
Phase-Locked Loop.
s
On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
s
Two low power modes, Idle and Power-down.
s
Processor wake-up from Power-down mode via external interrupt.
s
Individual enable/disable of peripheral functions for power optimization.
s
Dual power supply:
x
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
8.3%).
x
I/O power supply range of 3.0 V to 3.6 V (3.3 V
10%) with 5 V tolerant I/O
pads.
3.
Ordering information
3.1 Ordering options
Table 1:
Ordering information
Type number
Package
Name
Description
Version
LPC2104BBD48
LQFP48
plastic low profile quad flat package, 48 leads,
body 7
7
1.4 mm
SOT313-2
LPC2105BBD48
LQFP48
plastic low profile quad flat package, 48 leads,
body 7
7
1.4 mm
SOT313-2
LPC2106BBD48
LQFP48
plastic low profile quad flat package, 48 leads,
body 7
7
1.4 mm
SOT313-2
LPC2106FHN48
HVQFN48 plastic thermal enhanced very thin quad flat
package, no leads, 48 terminals, body
7
7
0.85
SOT619-1
Table 2:
Part options
Type number
Flash memory
RAM
Temperature range
LPC2104BBD48
128 kB
16 kB
0 to +70, LQFP
LPC2105BBD48
128 kB
32 kB
0 to +70, LQFP
LPC2106BBD48
128 kB
64 kB
0 to +70, LQFP
LPC2106FHN48
128 kB
60 kB
-
40 to +85, HVQFN
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 -- 05 February 2004
3 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
4.
Block diagram
(1) When test/debug interface is used, GPIO/other function sharing these pins are not available.
(2) APB with Ready signal.
Fig 1.
Block diagram.
INTERNAL
FLASH
CONTROLLER
002aaa412
AHB BRIDGE
EMULATION TRACE
MODULE
TEST/DEBUG
INTERFACE
AHB
DECODER
AHB TO VPB
BRIDGE
VPB
DIVIDER
VECTORED INTERRUPT
CONTROLLER
SYSTEM
FUNCTIONS
PLL
system
clock
SCL*
GPIO (32 PINS)
PWM1..6*
SDA*
TRST
(1)
TMS
(1)
TCK
(1)
TDI
(1)
TDO
(1)
RTCK
XTAL2
XTAL1
RST
V
DD
V
SS
SCK*
MOSI*
MISO*
EINT0*
EINT1*
EINT2*
CAP0..2*
MAT0..2*
CAP0..3*
MAT0..3*
SSEL*
TxD*
RxD*
TxD*
RxD*
MODEM CONTROL
(6 PINS)*
SPI SERIAL
INTERFACE
I2C SERIAL
INTERFACE
UART0
UART1
WATCHDOG
TIMER
SYSTEM
CONTROL
EXTERNAL
INTERRUPTS
GENERAL
PURPOSE I/O
REAL TIME
CLOCK
CAPTURE/
COMPARE
TIMER 0
CAPTURE/
COMPARE
TIMER 1
PWM0
AMBA AHB
(Advanced High-performance Bus)
128 kB
FLASH
ARM7TDMI-S
INTERNAL SRAM
CONTROLLER
16/32/64 kB
SRAM
ARM7 LOCAL BUS
APB(2)
*Shared with GPIO
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 -- 05 February 2004
4 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.
Pinning information
5.1 Pinning
Fig 2.
Pinning.
handbook, full pagewidth
LPC2104/2105/2106
002aaa411
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
P0.18/CAP1.3/TMS
P0.17/CAP1.2/TRST
P0.16/EINT0/MAT0.2
P0.15/RI1/EINT2
P0.14/DCD1/EINT1
V
SS4
NC
P0.13/DTR1/MAT1.1
V
DD3-1
(I/O)
P0.26/TRACESYNC
P0.25/PIPESTAT2
P0.12/DSR1/MAT1.0
P0.0/TxD0/PWM1
P0.1/RxD0/PWM3
P0.30/TRACEPKT3/TDI
P0.31/EXTIN0/TDO
V
DD3-2
(I/O)
P0.2/SCL/CAP0.0
V
SS2
NC
P0.3/SDA/MAT0.0
P0.4/SCK/CAP0.1
P0.5/MISO/MAT0.1
P0.6/MOSI/CAP0.2
P0.19/MAT1.2/TCK
P0.20/MAT1.3/TDI
P0.21/PWM5/TDO
NC
VDD1.8 (CORE)
RST
VSS1
P0.27/TRACEPKT0/TRST
P0.28/TRACEPKT1/TMS
P0.29/TRACEPKT2/TCK
X1
X2
P0.11/CTS1/CAP1.1
P0.10/RTS1/CAP1.0
P0.24/PIPESTAT1
P0.23/PIPESTAT0
P0.22/TRACECLK
VSS3
P0.9/RxD1/PWM6
P0.8/TxD1/PWM4
P0.7/SSEL/PWM2
DBGSEL
RTCK
NC
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 -- 05 February 2004
5 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.2 Pin description
Table 3:
Pin description
Symbol
Pin
Type
Description
P0.0 to P0.31
13, 14, 18,
21-24, 28-30,
35-37, 41,
44-48, 1-3,
32-34, 38,
39, 8-10, 15,
16
I/O
Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 0 pins depends upon the pin
function selected via the Pin Connect Block.
13
I/O
P0.0 -- Port 0 bit 0.
O
TxD0 -- Transmitter output for UART 0.
O
PWM1 -- Pulse Width Modulator output 1.
14
I/O
P0.1 -- Port 0 bit 1.
I
RxD0 -- Receiver input for UART 0.
O
PWM3 -- Pulse Width Modulator output 3.
18
I/O
P0.2 -- Port 0 bit 2.
I/O
SCL -- I
2
C clock input/output. Open drain output (for I
2
C compliance).
I
CAP0.0 -- Capture input for Timer 0, channel 0.
21
I/O
P0.3 -- Port 0 bit 3.
I/O
SDA -- I
2
C data input/output. Open drain output (for I
2
C compliance).
O
MAT0.0 -- Match output for Timer 0, channel 0.
22
I/O
P0.4 -- Port 0 bit 4.
I/O
SCK -- Serial clock. SPI clock output from master or input to slave.
I
CAP0.1 -- Capture input for Timer 0, channel 1.
23
I/O
P0.5 -- Port 0 bit 5.
I/O
MISO -- Master In Slave Out. Data input to SPI master or data output from
SPI slave.
O
MAT0.1 -- Match output for Timer 0, channel 1.
24
I/O
P0.6 -- Port 0 bit 6.
I/O
MOSI -- Master Out Slave In. Data output from SPI master or data input to
SPI slave.
I
CAP0.2 -- Capture input for Timer 0, channel 2.
28
I/O
P0.7 -- Port 0 bit 7.
I
SSEL -- Slave Select. Selects the SPI interface as a slave.
O
PWM2 -- Pulse Width Modulator output 2.
29
I/O
P0.8 -- Port 0 bit 8.
O
TxD1 -- Transmitter output for UART 1.
O
PWM4 -- Pulse Width Modulator output 4.
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