DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT85
4-bit magnitude comparator
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
FEATURES
Serial or parallel expansion without extra gating
Magnitude comparison of any binary words
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT85 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT85 are 4-bit magnitude comparators that
can be expanded to almost any length. They perform
comparison of two 4-bit binary, BCD or other monotonic
codes and present the three possible magnitude results at
the outputs (Q
A
>
B
, Q
A=B
and Q
A
<
B
). The 4-bit inputs are
weighted (A
0
to A
3
and B
0
to B
3
), where A
3
and B
3
are the
most significant bits.
The operation of the "85" is described in the function table,
showing all possible logic conditions. The upper part of the
table describes the normal operation under all conditions
that will occur in a single device or in a series expansion
scheme. In the upper part of the table the three outputs are
mutually exclusive. In the lower part of the table, the
outputs reflect the feed forward conditions that exist in the
parallel expansion scheme.
For proper compare operation the expander inputs (I
A
>
B
,
I
A=B
and I
A
<
B
) to the least significant position must be
connected as follows: I
A
<
B
= I
A
>
B
= = LOW and
I
A=B
= HIGH.
For words greater than 4-bits, units can be cascaded by
connecting outputs Q
A
<
B
, Q
A
>
and Q
A=B
to the
corresponding inputs of the significant comparator.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
A
n
, B
n
to Q
A
>
B
, Q
A
<
B
20
22
ns
A
n
, B
n
to Q
A=B
18
20
ns
I
A
<
B,
, I
A=B
, I
A
>
B
to Q
A
<
B
, Q
A
>
B
15
15
ns
I
A=B
to Q
A=B
11
15
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
18
20
pF
December 1990
4
Philips Semiconductors
Product specification
4-bit magnitude comparator
74HC/HCT85
APPLICATIONS
Process controllers
Servo-motor control
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
COMPARING INPUTS
CASCADING INPUTS
OUTPUTS
A
3
, B
3
A
2
, B
2
A
1
, B
1
A
0
, B
0
I
A
>
B
I
A
<
B
I
A=B
Q
A
>
B
Q
A
<
B
Q
A=B
A
3
>
B
3
A
3
<
B
3
A
3
=B
3
A
3
=B
3
X
X
A
2
>
B
2
A
2
<
B
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
1
>
B
1
A
1
<
B
1
A
1
=B
1
A
1
=B
1
X
X
A
0
>
B
0
A
0
<
B
0
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
1
=B
1
A
1
=B
1
A
1
=B
1
A
0
=B
0
A
0
=B
0
A
0
=B
0
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
H
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
1
=B
1
A
1
=B
1
A
1
=B
1
A
0
=B
0
A
0
=B
0
A
0
=B
0
X
H
L
X
H
L
H
L
L
L
L
H
L
L
H
H
L
L
Fig.4 Functional diagram.
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