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Электронный компонент: 74HC/HCT280

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT280
9-bit odd/even parity
generator/checker
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
9-bit odd/even parity generator/checker
74HC/HCT280
FEATURES
Word-length easily expanded by cascading
Similar pin configuration to the "180" for easy system
up-grading
Generates either odd or even parity for nine data bits
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT280 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT280 are 9-bit parity generators or checkers
commonly used to detect errors in high-speed data
transmission or data retrieval systems. Both even and odd
parity outputs are available for generating or checking
even or odd parity up to 9 bits.
The even parity output (
E
) is HIGH when an even number
of data inputs (I
0
to I
8
) are HIGH. The odd parity output (
0
)
is HIGH when an odd number of data inputs are HIGH.
Expansion to larger word sizes is accomplished by tying
the even outputs (
E
) of up to nine parallel devices to the
data inputs of the final stage. For a single-chip 16-bit
even/odd parity generator/checker, see
PC74HC/HCT7080.
APPLICATIONS
25-line parity generator/checker
81-line parity generator/checker
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
I
n
to
E
17
18
ns
I
n
to
O
20
22
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipationcapacitance per package
notes 1 and 2
65
65
pF
December 1990
3
Philips Semiconductors
Product specification
9-bit odd/even parity generator/checker
74HC/HCT280
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
8, 9, 10, 11, 12, 13, 1, 2, 4
I
0
to I
8
data inputs
5, 6
E
,
O
parity outputs
7
GND
ground (0 V)
14
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
9-bit odd/even parity generator/checker
74HC/HCT280
Fig.4 Functional diagram.
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
INPUTS
OUTPUTS
number of HIGH data
inputs (I
0
to I
8
)
E
O
even
odd
H
L
L
H
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
9-bit odd/even parity generator/checker
74HC/HCT280
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Out put capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
I
n
to
E
55
20
16
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
I
n
to
O
63
23
18
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6