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Электронный компонент: 74ABT899

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Philips
Semiconductors
74ABT899
9-bit dual latch transceiver with 8-bit
parity generator/checker (3-State)
Product specification
1998 Jan 16
INTEGRATED CIRCUITS
Supersedes data of 1993 Oct 04
IC23 Data Handbook
Philips Semiconductors
Product specification
74ABT899
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
2
1998 Jan 16
853-1623 18864
FEATURES
Symmetrical (A and B bus functions are identical)
Selectable generate parity or "feed-through" parity for A-to-B and
B-to-A directions
Independent transparent latches for A-to-B and B-to-A directions
Selectable ODD/EVEN parity
Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
Ability to simultaneously generate and check parity
Can simultaneously read/latch A and B bus data
Output capability: +64 mA/32mA
Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power up 3-State
Power-up reset
Live insertion/extraction permitted
DESCRIPTION
The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate
transparent latches for the A bus and B bus. Either bus can
generate or check parity. The parity bit can be fed-through with no
change or the generated parity can be substituted with the SEL
input.
Parity error checking of the A and B bus latches is continuously
provided with ERRA and ERRB, even with both buses in 3-State.
The 74ABT899 features independent latch enables for the A and B
bus latches, a select pin for ODD/EVEN parity, and separate error
signal output pins for checking parity.
FUNCTIONAL DESCRIPTION
The 74ABT899 has three principal modes of operation which are
outlined below. All modes apply to both the A-to-B and B-to-A
directions.
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL) is Low, the parity generated from
A0-A7 and B0-B7 can be checked and monitored by ERRA and
ERRB. (Fault detection on both input and output buses.)
Transparent latch, Feed-through parity, Check A and B bus
parity:
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
Independent latch enables (LEA and LEB) allow other permutations of:
Transparent latch / 1 bus latched / both buses latched
Feed-through parity / generate parity
Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50pF; V
CC
= 5V
2.9
ns
t
PLH
t
PHL
Propagation delay
An to ERRA
C
L
= 50pF; V
CC
= 5V
6.1
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
I/O
Output capacitance
Outputs disabled; V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
=5.5V
50
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
28-Pin Plastic PLCC
40
C to +85
C
74ABT899 A
74ABT899 A
SOT261-3
28-Pin Plastic SOP
40
C to +85
C
74ABT899 D
74ABT899 D
SOT136-1
28-Pin Plastic SSOP
40
C to +85
C
74ABT899 DB
74ABT899 DB
SOT341-1
Philips Semiconductors
Product specification
74ABT899
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
1998 Jan 16
3
PIN CONFIGURATION
3
4
5
6
7
8
9
10
11
12
17
18
19
20
21
22
23
24
25
26
LEA
A0
A1
A2
A3
A4
A5
A6
A7
BPAR
APAR
B7
B6
B5
B4
B3
B2
B1
B0
LEB
13
16
OEA
SEL
14
15
GND
ERRB
TOP VIEW
1
2
27
28
ODD/EVEN
ERRA
OEB
VCC
SA00289
PIN DESCRIPTION
SYMBOL
PIN
NUMBER
NAME AND FUNCTION
A0 - A7
4, 5, 6, 7,
8, 9, 10,
11
Latched A bus 3-State inputs/outputs
B0 - B7
19, 20,
21, 22,
23, 24,
25, 26
Latched B bus 3-State inputs/outputs
APAR
12
A bus parity 3-State input
BPAR
18
B bus parity 3-State input
ODD/
EVEN
1
Parity select input (Low for EVEN
parity)
OEA, OEB
13, 27
Output enable inputs (gate A to B,
B to A)
SEL
16
Mode select input (Low for generate)
LEA, LEB
3, 17
Latch enable inputs (transparent High)
ERRA,
ERRB
2, 15
Error signal outputs (active-Low)
GND
14
Ground (0V)
V
CC
28
Positive supply voltage
PLCC PIN CONFIGURATION
3
4
5
17
18
28
LEA
A0
A1
A2
A3
A4
A5
A6
A7
BPAR
VCC
LEB
16 SEL
15 ERRB
1
2
27
26
ODD/
EVEN
ERRA
OEB
B0
6
7
8
9
10
11
13
14 GND
OEA
12 APAR
25
B1
B2
B3
B4
B5
B6
B7
24
23
22 21
20
19
SA00291
LOGIC SYMBOL
4
5
6
7
8
9
10 11
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
26 25 24 23 22 21 20 19
2
15
3
16
17
1
LEA
SEL
LEB
ODD/EVEN
ERRA
ERRB
12
APAR
BPAR
18
27
13
OEB
OEA
SA00290
Philips Semiconductors
Product specification
74ABT899
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
1998 Jan 16
4
4
5
1
0
mux
9bit
Output
Buffer
OE
9bit
Output
Buffer
9bit
Transparent
Latch
LE
Parity
Generator
Parity
Generator
1
0
mux
OE
9bit
Transparent
Latch
LE
27
3
6
7
8
9
10
11
12
16
1
17
13
26
24
23
25
22
21
20
19
18
2
15
OEB
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
OEA
SEL
ODD/
EVEN
LEB
B7
BPAR
B6
B5
B4
B3
B2
B1
B0
ERRA
ERRB
SA00292
FUNCTION TABLE
INPUTS
OPERATING MODE
OEB
OEA
SEL
LEA
LEB
H
H
X
X
X
3-State A bus and B bus (input A & B simultaneously)
H
L
L
L
H
B
A, transparent B latch, generate parity from B0 - B7, check B bus parity
H
L
L
H
H
B
A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
H
L
L
X
L
B
A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
H
L
H
X
H
B
A, transparent B latch, parity feed-through, check B bus parity
H
L
H
H
H
B
A, transparent A & B latch, parity feed-through, check A & B bus parity
L
H
L
H
X
A
B, transparent A latch, generate parity from A0 - A7, check A bus parity
L
H
L
H
H
A
B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
L
H
L
L
X
A
B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
L
H
H
H
L
A
B, transparent A latch, parity feed-through, check A bus parity
L
H
H
H
H
A
B, transparent A & B latch, parity feed-through, check A & B bus parity
L
L
X
X
X
Output to A bus and B bus (NOT ALLOWED)
H = High voltage level
L
= Low voltage level
X = Don't care
Philips Semiconductors
Product specification
74ABT899
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
1998 Jan 16
5
PARITY AND ERROR FUNCTION TABLE
INPUTS
OUTPUTS
SEL
ODD/EVEN
xPAR
(A or B)
of High
Inputs
xPAR
(B or A)
ERRt
ERRr*
PARITY MODES
H
H
H
Even
Odd
H
H
H
L
H
L
Odd
H
H
L
Even
Odd
L
L
L
H
L
H
Mode
Feed-through/check parity
H
L
H
Even
Odd
H
H
L
H
L
H
Even
H
L
L
Even
Odd
L
L
H
L
H
L
Mode
L
H
H
Even
Odd
H
L
H
L
H
H
Odd
L
H
L
Even
Odd
H
L
L
H
H
H
Mode
Generate parity
L
L
H
Even
Odd
L
H
L
H
H
H
Even
L
L
L
Even
Odd
L
H
H
L
H
H
Mode
H = High voltage level
L
= Low voltage level
t
= Transmitif the data path is from A
B then ERRt is ERRA
r
= Receiveif the data path is from A
B then ERRr is ERRB
*
Blocked if latch is not transparent
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.