TL H 11924
TP3404
Quad
Digital
Adapter
for
Subscriber
Loops
(QDASL)
PRELIMINARY
July 1994
TP3404
Quad Digital Adapter for Subscriber Loops (QDASL)
General Description
The TP3404 is a combination 4-line transceiver for voice
and data transmission on twisted pair subscriber loops typi-
cally in PBX line card applications It is a companion device
to the TP3401 2 3 DASL single-channel transceivers In
addition to 4 independent transceivers a time-slot assign-
ment circuit is included to support interfacing to the system
backplane
Each QDASL line operates as an ISDN ``U'' Interface for
short loop applications typically in a PBX environment pro-
viding transmission for 2 B channels and 1 D channel
Full-duplex transmission at 144 kb s is achieved on single
twisted wire pairs using a burst-mode technique (Time Com-
pression Multiplexed) All timing sequences necessary for
loop activation and de-activation are generated on-chip
Alternate Mark Inversion (AMI) line coding is used to ensure
low error rates in the presence of noise with lower emi radia-
tion than other codes such as Biphase (Manchester) On
24 AWG cable the range is at least 1 8 km (6k ft)
Features
4 COMPLETE ISDN PBX 2-WIRE DATA TRANSCEIVERS
INCLUDING
Y
Quad 2 B plus D channel interface for PBX ``U''
interface
Y
144 kb s full-duplex on 1 twisted pair using Burst Mode
Transmission Technique
Y
Loop range up to 6 kft ( 24AWG)
Y
Alternate Mark Inversion coding with transmit Pulse
Shaping DAC Smoothing Filter and scrambler for low
emi radiation
Y
Adaptive line equalizer
Y
On-chip timing recovery no external components
Y
Programmable Time-Slot Assignment TDM interface for
B channels
Y
Separate interface for D channel with Programmable
Sub-Slot Assignment
Y
4 096 MHz master clock
Y
4 loop-back test modes
Y
MICROWIRE
TM
compatible serial control interface
Y
5V operation
Y
28-pin PLCC package
Block Diagram
TL H 11924 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
MICROWIRE
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
V
DDA
V
DDD
to GNDA GNDD
7V
Voltage at Any Li Lo Pin
V
CC
a
1V to GND
b
1V
Current at Any Lo
g
100 mA
Voltage at Any Digital Input
V
CC
a
1V to GND
b
1V
Current at Any Digital Output
g
50 mA
Storage Temperature Range
b
65 C to
a
150 C
Lead Temperature (Soldering 10 sec )
300 C
Electrical Characteristics
Unless otherwise specified limits printed in BOLD characters are guaranteed for
V
CCA
e
V
CCD
e
5V
g
5% T
A
e
0 C to
a
70 C Typical characteristics are specified at V
DDA
e
V
DDD
e
5 0V T
A
e
25 C All
signals are referenced to GND which is the common of GNDA and GNDD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACES
V
IH
Input High Voltage
All Digital Inputs (DC)
2
V
V
IL
Input Low Voltage
All Digital Inputs (DC)
0 8
V
V
OH
Output High Voltage
I
L
e a
1 mA
2 4
V
V
OL
Output Low Voltage
I
L
e b
1 mA
0 4
V
I
IL
Input Low Current
All Digital Input GND
k
V
IN
k
V
IL
b
10
10
m
A
I
IH
Input High Current
All Digital Input V
IH
k
V
IN
k
V
CC
b
10
10
m
A
I
OZ
Output Current in High Impedance
BO CO and DO
b
10
10
m
A
(TRl-STATE )
LINE INTERFACES
R
Li
Input Resistance
0V
k
V
Li
k
V
CC
20
kX
C
LLo
Load Capacitance
From Lo to GND
200
pF
ROLS
Output Resistance
Load
e
60X in Series with 2 mF to GND
3
X
V
DC
Mean DC Voltage at Lo
Load
e
200X in Series with 2 mF to GND
1 75
2 25
V
Voltage at LS
a
LS
b
POWER DISSIPATION
I
CC
0
Power Down Current
BCLK
e
0 Hz MCLK
e
0 Hz CCLK
e
0 Hz
10
mA
I
CC
1
Power Up Current
All 4 Channels Activated
75
mA
TRANSMISSION PERFORMANCE
Transmit Pulse Amplitude at Lo
R
L
e
200X in Series with 2 mF to GND
1 1
1 3
1 5
Vpk
Input Pulse Amplitude at Li
g
60
mVpk
TIMING SPECIFICATIONS
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MASTER CLOCK INPUT SPECIFICATIONS
f
MCLK
Frequency of MCLK
4 096
MHz
Master Clock Tolerance
Relative 2X MCLK in Slave
b
100
a
100
ppm
t
WMH
Period of MCLK High
Measured from V
IH
to V
IH
70
ns
t
WML
Period of MCLK Low
Measured from V
IL
to V
IL
70
ns
t
RM
Rise Time of MCLK
Measured from V
IL
to V
IH
15
ns
t
FM
Fall Time of MCLK
Measured from V
IH
to V
IL
15
ns
2
Electrical Characteristics
Unless otherwise specified limits printed in BOLD characters are guaranteed for
V
CCA
e
V
CCD
e
5V
g
5% T
A
e
0 C to
a
70 C Typical characteristics are specified at V
DDA
e
V
DDD
e
5 0V T
A
e
25 C All
signals are referenced to GND which is the common of GNDA and GNDD (Continued)
TIMING SPECIFICATIONS
(Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACE TIMING
f
BCLK
BCLK Frequency
4 096
4 1
MHz
t
WBH
Clock Pulse Width High
Measured from V
IH
to V
IH
70
ns
t
WBL
and Low for BCLK
Measured from V
IL
to V
IL
70
t
RB
Rise Time and Fall Time
Measured from V
IL
to V
IH
15
ns
t
FB
of BCLK
Measured from V
IH
to V
IL
15
t
HBM
BCLK Transition to MCLK High or Low
b
30
30
ns
t
SFC
Set up Time FS Valid to BCLK Invalid
20
4
ns
t
HCF
Hold Time BCLK Low to FS Invalid
40
30
ns
t
SBC
Setup Time BI Valid to BCLK Invalid
30
11
ns
t
HCB
Hold Time BCLK Valid to BI Invalid
40
7
ns
t
SDC
Setup Time DI Valid to BCLK Low
30
ns
t
HCD
Hold Time BCLK Low to DI Invalid
40
ns
t
DCB
Delay Time BCLK High to BO Valid
Load
e
2 LSTTL
a
100 pF
80
ns
t
DCBZ
Delay Time BCLK Low to BO High-Z
80
120
ns
t
DCD
Delay Time BCLK High to DO valid
Load
e
2 LSTTL
a
100 pF
80
ns
t
DCZ
Delay Time BCLK Low to DO High
40
120
ns
Impedance
t
DCT
Delay Time BCLK High to TSB Low
120
ns
t
ZBT
Disable Time BCLK Low to TSB High-Z
120
ns
MICROWIRE CONTROL INTERFACE TIMING
f
CCLK
Frequency of CCLK
2 1
MHz
t
CH
Period of CCLK High
Measured from V
IH
to V
IH
150
ns
t
CL
Period of CCLK Low
Measured from V
IL
to V
IL
150
ns
t
SSC
Setup Time CS Low to CCLK High
50
ns
t
HCS
Hold Time CCLK High to CS Transition
40
ns
t
SIC
Setup Time CI Valid to CCLK High
50
ns
t
HCI
Hold Time CCLK High to CI Invalid
20
ns
t
DCO
Delay Time CCLK Low to CO Valid
80
ns
t
DSOZ
Delay Time CS High to CO High-Z
80
ns
t
DCIZ
Delay Time CCLK to INT High-Z
100
ns
Notes
For the purposes of this specification the following conditions apply
a All input signals are defined as V
IL
e
0 4V V
IH
e
2 7V t
r
k
10 ns t
f
k
10 ns
b Delay times are measured from the input signal Valid to the output signal Valid
c Setup times are measured from the Data input Valid to the clock input Invalid
d Hold times are measured from the clock signal Valid to the Data input Invalid
3
Pin Descriptions
Pin
Pin
Description
No
Name
1
GNDA
Analog Ground or 0V All analog signals are referenced to this pin
15
GNDD
Digital Ground 0V It must connect to GNDA with a shortest possible trace This can be done directly
underneath the part
28
VDDA
Positive power supply input to QDASL analog section It must be 5V
g
5%
16
VDDD
Positive power supply input to QDASL digital section It must be 5V
g
5% and connect to VDDA with the
shortest possible trace This can be done directly underneath the part
11
FS
Frame Sync input this signal is the 8 kHz clock which defines the start of the transmit and receive frames at the
digital interfaces
9
MCLK
This pin is the 4 096 MHz Master Clock input which requires a CMOS logic level clock from a stable source
MCLK must be synchronous with BCLK
10
BCLK
Bit Clock logic input which determines the data shift rate for B and D channel data at the BI BO DI and DO
pins BCLK may be any multiple of 8 kHz from 256 kHz to 4 096 MHz but must be synchronous with MCLK
12
BI
Time-division multiplexed input for B1 and B2 channel data to be transmitted to the 4 lines Data on this pin is
shifted in on the failing edge of BCLK into the B1 and B2 channels during the selected transmit time-slots
13
BO
Time-division multiplexed receive data output bus B1 and B2 channel data from all 4 lines is shifted out on the
rising edge of BCLK on this pin during the assigned receive time-slots At all other times this output is
TRI-STATE (high impedance)
14
TSB
This pin is an open-drain output which is normally high impedance but pulls low during any active B channel
receive time slots at the BO pin
7
DI
Time-division multiplexed input for D channel data to be transmitted to the 4 lines Data on this pin is shifted in
on the failing edge of BCLK into the D channel during the selected transmit sub-time-slots
8
DO
Time-division multiplexed output for D channel data received from the 4 lines Data on this pin is shifted out on
the rising edge of BCLK during the selected receive sub-time-slot
19
CCLK
Microwire Control Clock input This clock shifts serial control information into CI and out from CO when the CS
input is low depending on the current instruction CCLK may be asynchronous with the other system clocks
21
CI
Control data Input Serial control information is shifted into the QDASL on this pin on the rising edges of CCLK
when CS is low
17
INT
Interrupt request output a latched output signal which is normally high impedance and goes low to indicate a
change of status of any of the 4 loop transmission systems This latch is cleared when the Status Register is
read by the microprocessor Bipolar Violation does not effect this output
20
CO
Control data Output Serial control status information is shifted out from the QDASL on this pin on the falling
edges of CCLK when CS is low
18
CS
Chip Select input When this pin is pulled low the Microwire interface is enabled to allow control information to
be written in to and out from the device via the CI and CO ins When high this pin inhibits the Microwire
interface
4
Lo0
Line driver transmit outputs for the 4 transmission channels Each output is an amplifier intended to drive a
transformer
3
Lo1
26
Lo2
25
Lo3
5
Li0
Line receive amplifier inputs for the 4 transmission channels Each Li pin is a self-biased high impedance input
which should be connected to the transformer via the recommended line interface circuit
2
Li1
27
Li2
24
Li3
4
Connection Diagram
TL H 11924 2
Top View
Order Number TP3404V
See NS Package Number V28A
Functional Description
The QDASL contains 4 transceivers each of which can in-
teroperate with any of the TP340X family of single-channel
DASL transceivers Each QDASL transceiver has its own
independent line transmit and receive section timing recov-
ery circuit scrambler descrambler and loop activation con-
troller Functions which are shared by the 4 transceivers
include the Microwire control port and the digital interface
with time-slot assignment
BURST MODE OPERATION
For full-duplex operation over a single twisted-pair burst
mode timing is used with the QDASL end of each line act-
ing as the loop timing master and the DASL at the terminal
being the timing slave (the QDASL transceivers cannot op-
erate in loop timing slave mode)
Each burst within a DASL line is initiated by the QDASL
Master transmitting a startbit for burst framing followed by
the B1 B2 and D channel data from 2 consecutive 8 kHz
frames combined in the format shown in
Figure 1 During
transmit bursts the receiver input for that channel is inhibit-
ed to avoid disturbing the adaptive circuits The slave's re-
ceiver is enabled at this time and it synchronizes to the start
bit of the burst which is always an unscrambled ``1'' (of the
opposite polarity to the last ``1'' sent in the previous burst)
When the slave detects that 36 bits following the start bit
have been received it disables the received input waits 6
line symbol periods to match the other end settling guard
time and then begins to transmit its burst back towards the
master which by this time has enabled its receiver input
The burst repetition rate is thus 4 KHz
LINE TRANSMIT SECTIONS
Alternate Mark Inversion (AMI) line coding in which binary
``1''s are alternately transmitted as a positive pulse then a
negative pulse is used on each DASL line because of its
spectral efficiency and null DC energy content All transmit-
ted bits excluding the start bit are scrambled by a 9-bit
scrambler to provide good spectral spreading with a strong
timing content The scrambler feedback polynomial is X
9
a
X
5
a
1
TL H 11924 3
FIGURE 1 Burst Mode Timing on the Line
5
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