TP3054-X, TP3057-X
Extended Temperature Serial Interface CODEC/Filter
COMBO
Family
General Description
The TP3054, TP3057 family consists of -law and A-law
monolithic PCM CODEC/filters utilizing the A/D and D/A
conversion architecture shown in Figure 1, and a serial PCM
interface. The devices are fabricated using National's ad-
vanced double-poly CMOS process (microCMOS).
The encode portion of each device consists of an input gain
adjust amplifier, an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz. Also included are auto-zero circuitry and a com-
panding coder which samples the filtered signal and en-
codes it in the companded -law or A-law PCM format. The
decode portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the com-
panded -law or A-law code, a low-pass filter which corrects
for the sin x/x response of the decoder output and rejects
signals above 3400 Hz followed by a single-ended power
amplifier capable of driving low impedance loads. The de-
vices require two 1.536 MHz, 1.544 MHz or 2.048 MHz
transmit and receive master clocks, which may be asynchro-
nous; transmit and receive bit clocks, which may vary from
64 kHz to 2.048 MHz; and transmit and receive frame sync
pulses. The timing of the frame sync pulses and PCM data is
compatible with both industry standard formats.
Features
n
-40C to +85C operation
n
Complete CODEC and filtering system (COMBO)
including:
-- Transmit high-pass and low-pass filtering
-- Receive low-pass filter with sin x/x correction
-- Active RC noise filters
-- -law or A-law compatible COder and DECoder
-- Internal precision voltage reference
-- Serial I/O interface
-- Internal auto-zero circuitry
n
-law, 16-pin -- TP3054
n
A-law, 16-pin -- TP3057
n
Designed for D3/D4 and CCITT applications
n
5V operation
n
Low operating power -- typically 50 mW
n
Power-down standby mode -- typically 3 mW
n
Automatic power-down
n
TTL or CMOS compatible digital interfaces
n
Maximizes line interface card circuit density
n
Dual-In-Line or PCC surface mount packages
n
See also AN-370, "Techniques for Designing with
CODEC/Filter COMBO Circuits"
Connection Diagrams
Plastic Chip Carriers
00867408
Top View
Order Number TP3057V-X
NS Package Number V20A
Dual-In-Line Package
00867401
Top View
Order Number TP3054N-X
NS Package Number N16E
Order Number TP3054WM-X
NS Package Number M16B
COMBO
and TRI-STATE
are registered trademarks of National Semiconductor Corporation.
March 2005
TP3054-X,
TP3057-X
Extended
T
emperature
Serial
Interface
CODEC/Filter
COMBO
Family
2005 National Semiconductor Corporation
DS008674
www.national.com
Pin Descriptions
Symbol
Function
V
BB
Negative power supply pin.
V
BB
= -5V
5%.
GNDA
Analog ground. All signals are
referenced to this pin.
VF
R
O
Analog output of the receive power
amplifier.
V
CC
Positive power supply pin.
V
CC
= +5V
5%.
FS
R
Receive frame sync pulse which
enables BCLK
R
to shift PCM data into
D
R
. FS
R
is an 8 kHz pulse train. See
Figure 2 and Figure 3 for timing details.
D
R
Receive data input. PCM data is shifted
into D
R
following the FS
R
leading edge.
Symbol
Function
BCLK
R
/CLKSEL The bit clock which shifts data into D
R
after the FS
R
leading edge. May vary
from 64 kHz to 2.048 MHz.
Alternatively, may be a logic input
which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in
synchronous mode and BCLK
X
is used
for both transmit and receive directions
(see Table 1).
MCLK
R
/PDN
Receive master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
X
, but should
be synchronous with MCLK
X
for best
performance. When MCLK
R
is
connected continuously low, MCLK
X
is
selected for all internal timing. When
MCLK
R
is connected continuously high,
the device is powered down.
Block Diagram
00867402
FIGURE 1.
TP3054-X,
TP3057-X
www.national.com
2
Pin Descriptions
(Continued)
Symbol
Function
MCLK
X
Transmit master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
R
. Best
performance is realized from
synchronous operation.
FS
X
Transmit frame sync pulse input which
enables BCLK
X
to shift out the PCM
data on D
X
. FS
X
is an 8 kHz pulse
train, see Figure 2 and Figure 3 for
timing details.
BCLK
X
The bit clock which shifts out the PCM
data on D
X
. May vary from 64 kHz to
2.048 MHz, but must be synchronous
with MCLK
X
.
D
X
The TRI-STATE
PCM data output
which is enabled by FS
X
.
TS
X
Open drain output which pulses low
during the encoder time slot.
GS
X
Analog output of the transmit input
amplifier. Used to externally set gain.
VF
X
I
-
Inverting input of the transmit input
amplifier.
VF
X
I
+
Non-inverting input of the transmit input
amplifier.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initial-
izes the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the D
X
and VF
R
O
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK
R
/PDN pin and FS
X
and/or FS
R
pulses must be
present. Thus, 2 power-down control modes are available.
The first is to pull the MCLK
R
/PDN pin high; the alternative is
to hold both FS
X
and FS
R
inputs continuously low -- the
device will power-down approximately 1 ms after the last
FS
X
or FS
R
pulse. Power-up will occur on the first FS
X
or
FS
R
pulse. The TRI-STATE PCM data output, D
X
, will remain
in the high impedance state until the second FS
X
pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLK
X
and the MCLK
R
/PDN pin can be used as a power-down
control. A low level on MCLK
R
/PDN powers up the device
and a high level powers down the device. In either case,
MCLK
X
will be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be applied
to BCLK
X
and the BCLK
R
/CLKSEL can be used to select the
proper internal divider for a master clock of 1.536 MHz,
1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the
device automatically compensates for the 193rd clock pulse
each frame.
With a fixed level on the BCLK
R
/CLKSEL pin, BCLK
X
will be
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLK
R
/
CLKSEL. In this synchronous mode, the bit clock, BCLK
X
,
may be from 64 kHz to 2.048 MHz, but must be synchronous
with MCLK
X
.
Each FS
X
pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X
output on the positive edge of BCLK
X
. After 8 bit
clock periods, the TRI-STATE D
X
output is returned to a high
impedance state. With an FS
R
pulse, PCM data is latched
via the D
R
input on the negative edge of BCLK
X
(or BCLK
R
if running). FS
X
and FS
R
must be synchronous with
MCLK
X/R
.
TABLE 1. Selection of Master Clock Frequencies
BCLK
R
/CLKSEL
Master Clock
Frequency Selected
TP3057
TP3054
Clocked
2.048 MHz
1.536 MHz or
1.544 MHz
0
1.536 MHz or
2.048 MHz
1.544 MHz
1
2.048 MHz
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK
X
and MCLK
R
must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLK
R
should be synchronous
with MCLK
X
, which is easily achieved by applying only static
logic levels to the MCLK
R
/PDN pin. This will automatically
connect MCLK
X
to all internal MCLK
R
functions (see Pin
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FS
X
starts each encoding cycle and must be synchronous
with MCLK
X
and BCLK
X
. FS
R
starts each decoding cycle
and must be synchronous with BCLK
R
. BCLK
R
must be a
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK
X
and BCLK
R
may operate from
64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS
X
and FS
R
, must be one bit clock period long, with
timing relationships specified in Figure 2. With FS
X
high
during a falling edge of BCLK
X
, the next rising edge of
BCLK
X
enables the D
X
TRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the D
X
output. With FS
R
high during a falling edge
of BCLK
R
(BCLK
X
in synchronous mode), the next falling
edge of BCLK
R
latches in the sign bit. The following seven
falling edges latch in the seven remaining bits. All four de-
vices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode.
TP3054-X,
TP3057-X
www.national.com
3
Functional Description
(Continued)
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FS
X
and FS
R
, must be three or more bit clock periods long,
with timing relationships specified in Figure 3. Based on the
transmit frame sync, FS
X
, the COMBO will sense whether
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The D
X
TRI-STATE output buffer is
enabled with the rising edge of FS
X
or the rising edge of
BCLK
X
, whichever comes later, and the first bit clocked out
is the sign bit. The following seven BCLK
X
rising edges clock
out the remaining seven bits. The D
X
output is disabled by
the falling BCLK
X
edge following the eighth rising edge, or by
FS
X
going low, whichever comes later. A rising edge on the
receive frame sync pulse, FS
R
, will cause the PCM data at
D
R
to be latched in on the next eight falling edges of BCLK
R
(BCLK
X
in synchronous mode). All four devices may utilize
the long frame sync pulse in synchronous or asynchronous
mode.
In applications where the LSB bit is used for signalling, with
FS
R
two bit clock periods long, the decoder will interpret the
lost LSB as "
1
/
2
" to minimize noise and distortion.
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be realized.
The op amp drives a unity-gain filter consisting of RC active
pre-filter, followed by an eighth order switched-capacitor
bandpass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. The A/D
is of companding type according to -law (TP3054) or A-law
(TP3057) coding conventions. A precision voltage reference
is trimmed in manufacturing to provide an input overload
(t
MAX
) of nominally 2.5V peak (see table of Transmission
Characteristics). The FS
X
frame sync pulse controls the
sampling of the filter output, and then the successive-
approximation encoding cycle begins. The 8-bit code is then
loaded into a buffer and shifted out through D
X
at the next
FS
X
pulse. The total encoding delay will be approximately
165 s (due to the transmit filter) plus 125 s (due to encod-
ing delay), which totals 290 s. Any offset voltage due to the
filters or comparator is cancelled by sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter clocked
at 256 kHz. The decoder is A-law (TP3057) or -law
(TP3054) and the 5th order low pass filter corrects for the sin
x/x attenuation due to the 8 kHz sample/hold. The filter is
then followed by a 2nd order RC active post-filter/power
amplifier capable of driving a 600
load to a level of 7.2
dBm. The receive section is unity-gain. Upon the occurrence
of FS
R
, the data at the D
R
input is clocked in on the falling
edge of the next eight BCLK
R
(BCLK
X
) periods. At the end of
the decoder time slot, the decoding cycle begins, and 10 s
later the decoder DAC output is updated. The total decoder
delay is
10 s (decoder update) plus 110 s (filter delay)
plus 62.5 s (
1
/
2
frame), which gives approximately 180 s.
TP3054-X,
TP3057-X
www.national.com
4
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC
to GNDA
7V
V
BB
to GNDA
-7V
Voltage at any Analog Input
or Output
V
CC
+0.3V to V
BB
-0.3V
Voltage at any Digital Input or
Output
V
CC
+0.3V to GNDA-0.3V
Operating Temperature Range
-55C to + 125C
Storage Temperature Range
-65C to +150C
Lead Temperature
(Soldering, 10 sec.)
300C
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
= +5.0V
5%, V
BB
= -5.0V
5%; T
A
=
-40C to +85C by correlation with 100% electrical testing at T
A
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
CC
=
+5.0V, V
BB
= -5.0V, T
A
= 25C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACE
V
IL
Input Low Voltage
0.6
V
V
IH
Input High Voltage
2.2
V
V
OL
Output Low Voltage
D
X
, I
L
=3.2 mA
0.4
V
SIG
R
, I
L
=1.0 mA
0.4
V
TS
X
, I
L
=3.2 mA, Open Drain
0.4
V
V
OH
Output High Voltage
D
X
, I
H
=-3.2 mA
2.4
V
SIG
R
, I
H
=-1.0 mA
2.4
V
I
IL
Input Low Current
GNDA
V
IN
V
IL
, All Digital Inputs
-10
10
A
I
IH
Input High Current
V
IH
V
IN
V
CC
-10
10
A
I
OZ
Output Current in High Impedance
D
X
, GNDA
V
O
V
CC
-10
10
A
State (TRI-STATE)
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
I
I
XA
Input Leakage Current
-2.5V
V+2.5V, VF
X
I
+
or VF
X
I
-
-200
200
nA
R
I
XA
Input Resistance
-2.5V
V+2.5V, VF
X
I
+
or VF
X
I
-
10
M
R
O
XA
Output Resistance
Closed Loop, Unity Gain
1
3
R
L
XA
Load Resistance
GS
X
10
k
C
L
XA
Load Capacitance
GS
X
50
pF
V
O
XA
Output Dynamic Range
GS
X
, R
L
10 k
-2.8
2.8
V
A
V
XA
Voltage Gain
VF
X
I
+
to GS
X
5000
V/V
F
U
XA
Unity Gain Bandwidth
1
2
MHz
V
OS
XA
Offset Voltage
-20
20
mV
V
CM
XA
Common-Mode Voltage
CMRRXA
>
60 dB
-2.5
2.5
V
CMRRXA
Common-Mode Rejection Ratio
DC Test
60
dB
PSRRXA
Power Supply Rejection Ratio
DC Test
60
dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
R
O
RF
Output Resistance
Pin VF
R
O
1
3
R
L
RF
Load Resistance
VF
R
O=
2.5V
600
C
L
RF
Load Capacitance
500
pF
VOS
R
O
Output DC Offset Voltage
-200
200
mV
POWER DISSIPATION (ALL DEVICES)
I
CC
0
Power-Down Current
No Load (Note 2)
0.65
2.0
mA
I
BB
0
Power-Down Current
No Load (Note 2)
0.01
0.33
mA
I
CC
1
Power-Up (Active) Current
No Load( 40C to 85C)
5.0
11.0
mA
I
BB
1
Power-Up (Active) Current
No Load ( 40C to 85C)
5.0
11.0
mA
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: I
CC0
and I
BB0
are measured after first achieving a power-up state.
TP3054-X,
TP3057-X
www.national.com
5
Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
= +5.0V
5%, V
BB
= -5.0V
5%; T
A
=
-40C to +85C by correlation with 100% electrical testing at T
A
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
CC
=
+5.0V, V
BB
= 5.0V, T
A
= 25C. All timing parameters are assured at V
OH
= 2.0V and V
OL
= 0.7V. See Definitions and Timing
Conventions section for test methods information.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1/t
PM
Frequency of Master Clocks
Depends on the Device Used and the
1.536
MHz
BCLK
R
/CLKSEL Pin.
1.544
MHz
MCLK
X
and MCLK
R
2.048
MHz
t
RM
Rise Time of Master Clock
MCLK
X
and MCLK
R
50
ns
t
FM
Fall Time of Master Clock
MCLK
X
and MCLK
R
50
ns
t
PB
Period of Bit Clock
485
488
15725
ns
t
RB
Rise Time of Bit Clock
BCLK
X
and BCLK
R
50
ns
t
FB
Fall Time of Bit Clock
BCLK
X
and BCLK
R
50
ns
t
WMH
Width of Master Clock High
MCLK
X
and MCLK
R
160
ns
t
WML
Width of Master Clock Low
MCLK
X
and MCLK
R
160
ns
t
SBFM
Set-Up Time from BCLK
X
High
First Bit Clock after
Short Frame
100
ns
to MCLK
X
Falling Edge
the Leading Edge
of FS
X
Long Frame
125
t
SFFM
Setup Time from FS
X
High to
MCLK
X
Falling Edge
Long Frame Only
100
ns
t
WBH
Width of Bit Clock High
V
IH
=2.2V
160
ns
t
WBL
Width of Bit Clock Low
V
IL
=0.6V
160
ns
t
HBFL
Holding Time from Bit Clock
Long Frame Only
0
ns
Low to Frame Sync
t
HBFS
Holding Time from Bit Clock
Short Frame Only
0
ns
High to Frame Sync
t
SFB
Set-Up Time from Frame Sync
Long Frame Only
115
ns
to Bit Clock Low
t
DBD
Delay Time from BCLK
X
High
Load=150 pF plus 2 LSTTL Loads
0
140
ns
to Data Valid
t
DBTS
Delay Time to TS
X
Low
Load=150 pF plus 2 LSTTL Loads
140
ns
t
DZC
Delay Time from BCLK
X
Low to
C
L
=0 pF to 150 pF
50
165
ns
Data Output Disabled
t
DZF
Delay Time to Valid Data from
C
L
=0 pF to 150 pF
20
165
ns
FS
X
or BCLK
X
, Whichever
Comes Later
t
SDB
Set-Up Time from D
R
Valid to
50
ns
BCLK
R/X
Low
t
HBD
Hold Time from BCLK
R/X
Low to
50
ns
D
R
Invalid
t
SF
Set-Up Time from FS
X/R
to
Short Frame Sync Pulse (1 Bit Clock
50
ns
BCLK
X/R
Low
Period Long)
t
HF
Hold Time from BCLK
X/R
Low
Short Frame Sync Pulse (1 Bit Clock
100
ns
to FS
X/R
Low
Period Long)
t
HBFl
Hold Time from 3rd Period of
Long Frame Sync Pulse (from 3 to 8 Bit
100
ns
Bit Clock Low to Frame Sync
Clock Periods Long)
(FS
X
or FS
R
)
t
WFL
Minimum Width of the Frame
64k Bit/s Operating Mode
160
ns
Sync Pulse (Low Level)
TP3054-X,
TP3057-X
www.national.com
6
Timing
Diagrams
00867403
FIGURE
2.
Short
Frame
Sync
T
iming
TP3054-X,
TP3057-X
www.national.com
7
Timing
Diagrams
(Continued)
00867409
FIGURE
3.
Long
Frame
Sync
T
iming
TP3054-X,
TP3057-X
www.national.com
8
Transmission Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
= +5.0V
5%, V
BB
= -5.0V
5%; T
A
=
-40C to +85C by correlation with 100% electrical testing at T
A
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, V
IN
= 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at V
CC
= +5.0V, V
BB
= -5.0V, T
A
= 25C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
Nominal 0 dBm0 Level is 4 dBm
(Definition of nominal gain)
(600
)
0 dBm0
1.2276
Vrms
t
MAX
Max Overload Level
TP3054 (3.17 dBm0)
2.501
V
PK
TP3057 (3.14 dBm0)
2.492
V
PK
G
XA
Transmit Gain, Absolute
T
A
=25C, V
CC
=5V, V
BB
=-5V
Input at GS
x
=0 dBm0 at 1020 Hz
-0.15
0.15
dB
G
XR
Transmit Gain, Relative to G
XA
f=16 Hz
-40
dB
f=50 Hz
-30
dB
f=60 Hz
-26
dB
f=200 Hz
-1.8
-0.1
dB
f=300 Hz3000 Hz
-0.15
0.15
dB
f=3152 Hz
-0.15
0.20
dB
f=3300 Hz
-0.35
0.1
dB
f=3400 Hz
-0.7
0
dB
f=4000 Hz
-14
dB
f=4600 Hz and Up, Measure
-32
dB
Response from 0 Hz to 4000 Hz
G
XAT
Absolute Transmit Gain Variation
Relative to G
XA
-0.15
0.15
dB
with Temperature
G
XAV
Absolute Transmit Gain Variation
Relative to G
XA
-0.05
0.05
dB
with Supply Voltage
G
XRL
Transmit Gain Variations with
Sinusoidal Test Method
Level
Reference Level=-10 dBm0
VF
X
I
+
=-40 dBm0 to +3 dBm0
-0.2
0.2
dB
VF
X
I
+
=-50 dBm0 to -40 dBm0
-0.4
0.4
dB
VF
X
I
+
=-55 dBm0 to -50 dBm0
-1.2
1.2
dB
G
RA
Receive Gain, Absolute
T
A
=25C, V
CC
=5V, V
BB
=-5V
Input=Digital Code Sequence
for 0 dBm0 Signal at 1020 Hz
-0.20
0.20
dB
G
RR
Receive Gain, Relative to G
RA
f=0 Hz to 3000 Hz
-0.15
0.15
dB
f=3300 Hz
-0.35
0.1
dB
f=3400 Hz
-0.7
0
dB
f=4000 Hz
-14
dB
G
RAT
Absolute Receive Gain Variation
Relative to G
RA
-0.15
0.15
dB
with Temperature
G
RAV
Absolute Receive Gain Variation
Relative to G
RA
-0.05
0.05
dB
with Supply Voltage
G
RRL
Receive Gain Variations with
Sinusoidal Test Method; Reference
Level
Input PCM Code Corresponds to an
Ideally Encoded
PCM Level =-40 dBm0 to +3 dBm0
-0.2
0.2
dB
PCM Level =-50 dBm0 to -40 dBm0
-0.4
0.4
dB
PCM Level =-55 dBm0 to -50 dBm0
-1.2
1.2
dB
TP3054-X,
TP3057-X
www.national.com
9
Transmission Characteristics
(Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
= +5.0V
5%, V
BB
= -5.0V
5%; T
A
=
-40C to +85C by correlation with 100% electrical testing at T
A
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, V
IN
= 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at V
CC
= +5.0V, V
BB
= -5.0V, T
A
= 25C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
V
RO
Receive Output Drive Level
R
L
=600
-2.5
2.5
V
ENVELOPE DELAY DISTORTION WITH FREQUENCY
D
XA
Transmit Delay, Absolute
f=1600 Hz
290
315
s
D
XR
Transmit Delay, Relative to D
XA
f=500 Hz-600 Hz
195
220
s
f=600 Hz-800 Hz
120
145
s
f=800 Hz-1000 Hz
50
75
s
f=1000 Hz-1600 Hz
20
40
s
f=1600 Hz-2600 Hz
55
75
s
f=2600 Hz-2800 Hz
80
105
s
f=2800 Hz-3000 Hz
130
155
s
D
RA
Receive Delay, Absolute
f=1600 Hz
180
200
s
D
RR
Receive Delay, Relative to D
RA
f=500 Hz-1000 Hz
-40
-25
s
f=1000 Hz-1600 Hz
-30
-20
s
f=1600 Hz-2600 Hz
70
90
s
f=2600 Hz-2800 Hz
100
125
s
f=2800 Hz-3000 Hz
145
175
s
NOISE
N
XC
Transmit Noise, C Message
TP3054
12
16
dBrnC0
Weighted
(Note 3)
N
XP
Transmit Noise, P Message
TP3057
-74
-67
dBm0p
Weighted
(Note 3)
N
RC
Receive Noise, C Message
PCM Code is Alternating
Weighted
Positive and Negative Zero -- TP3054
8
11
dBrnC0
N
RP
Receive Noise, P Message
TP3057 PCM Code Equals Positive
Weighted
Zero --
-82
-79
dBm0p
N
RS
Noise, Single Frequency
f=0 kHz to 100 kHz, Loop Around
-53
dBm0
Measurement, VF
X
I
+
=0 Vrms
PPSR
X
Positive Power Supply Rejection,
V
CC
=5.0 V
DC
+100 mVrms
Transmit
f=0 kHz-50 kHz (Note 4)
40
dBC
NPSR
X
Negative Power Supply Rejection,
V
BB
=-5.0 V
DC
+ 100 mVrms
Transmit
f=0 kHz-50 kHz (Note 4)
40
dBC
PPSR
R
Positive Power Supply Rejection,
PCM Code Equals Positive Zero
Receive
V
CC
=5.0 V
DC
+100 mVrms
Measure VF
R
0
f=0 Hz-4000 Hz
38
dBC
f=4 kHz-25 kHz
38
dB
f=25 kHz-50 kHz
35
dB
NPSR
R
Negative Power Supply Rejection,
PCM Code Equals Positive Zero
Receive
V
BB
=-5.0 V
DC
+100 mVrms
Measure VF
R
0
f=0 Hz-4000 Hz
38
dBC
f=4 kHz-25 kHz
38
dB
f=25 kHz-50 kHz
35
dB
TP3054-X,
TP3057-X
www.national.com
10
Transmission Characteristics
(Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
= +5.0V
5%, V
BB
= -5.0V
5%; T
A
=
-40C to +85C by correlation with 100% electrical testing at T
A
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, V
IN
= 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at V
CC
= +5.0V, V
BB
= -5.0V, T
A
= 25C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
NOISE
SOS
Spurious Out-of-Band Signals
Loop Around Measurement, 0 dBm0,
-30
dB
at the Channel Output
300 Hz to 3400 Hz Input PCM Code
Applied at D
R
.
4600 Hz7600 Hz
-30
dB
7600 Hz8400 Hz
-40
dB
8400 Hz100,000 Hz
-30
dB
DISTORTION
STD
X,
Signal to Total Distortion
Sinusoidal Test Method (Note 6)
STD
R
Transmit or Receive
Level=3.0 dBm0
33
dBC
Half-Channel
=0 dBm0 to -30 dBm0
36
dBC
=-40 dBm0
XMT
28
dBC
RCV
29
dBC
=-55 dBm0
XMT
13
dBC
RCV
14
dBC
SFD
X
Single Frequency Distortion,
-43
dB
Transmit
SFD
R
Single Frequency Distortion,
-43
dB
Receive
IMD
Intermodulation Distortion
Loop Around Measurement,
-41
dB
VF
X
I
+
=-4 dBm0 to -21 dBm0, Two
Frequencies in the Range
300 Hz-3400 Hz
CROSSTALK
CT
X-R
Transmit to Receive Crosstalk,
f=300 Hz-3400 Hz
-90
-70
dB
0 dBm0 Transmit Level
D
R
=Quiet PCM Code (Note 6)
CT
R-X
Receive to Transmit Crosstalk,
f=300 Hz-3400 Hz, VF
X
I=Multitone
-90
-70
dB
0 dBm0 Receive Level
(Note 4)
ENCODING FORMAT AT D
X
OUTPUT
TP3054
TP3057
-Law
A-Law
(Includes Even Bit Inversion)
V
IN
(at GS
X
)=+Full-Scale
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
V
IN
(at GS
X
)=0V
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
V
IN
(at GS
X
)=-Full-Scale
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
Note 3: Measured by extrapolation from the distortion test result at -50 dBm0.
Note 4: PPSR
X
, NPSR
X
, and CT
RX
are measured with a -50 dBm0 activation signal applied to VF
X
I
+
.
Note 5: TP3054/57 are measured using C message weighted filter for -law and psophometric weighted filter for A-law.
Note 6: CT
XR
@ 1.544 MHz MCLK
X
freq. is -70 dB max. 50%
5% BCLK
X
duty cycle.
TP3054-X,
TP3057-X
www.national.com
11
Applications Information
POWER SUPPLIES
While the pins of the TP3050 family are well protected
against electrical misuse, it is recommended that the stan-
dard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a "hot" socket with power and clocks already
present, an extra long ground pin in the connector should be
used.
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 F supply decou-
pling capacitors should be connected from this common
ground point to V
CC
and V
BB
, as close to device pins as
possible.
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in star formation, rather than via a ground bus.
This common ground point should be decoupled to V
CC
and
V
BB
with 10 F capacitors.
RECEIVE GAIN ADJUSTMENT
For applications where a TP3050 family CODEC/filter re-
ceive output must drive a 600
load, but a peak swing lower
than
2.5V is required, the receive gain can be easily ad-
justed by inserting a matched T-pad or
-pad at the output.
Table 2 lists the required resistor values for 600
termina-
tions. As these are generally non-standard values, the equa-
tions can be used to compute the attenuation of the closest
practical set of resistors. It may be necessary to use unequal
values for the R1 or R4 arms of the attenuators to achieve a
precise attenuation. Generally it is tolerable to allow a small
deviation of the input impedance from nominal while still
maintaining a good return loss. For example a 30 dB return
loss against 600
is obtained if the output impedance of the
attenuator is in the range 282
to 319 (assuming a perfect
transformer).
T-Pad Attenuator
00867411
TP3054-X,
TP3057-X
www.national.com
12
Applications Information
(Continued)
-Pad Attenuator
00867412
Note: See Application Note 370 for further details.
TABLE 2. Attentuator Tables for Z1=Z2=300
(All Values in
)
dB
R1
R2
R3
R4
0.1
1.7
26k
3.5
52k
0.2
3.5
13k
6.9
26k
0.3
5.2
8.7k
10.4
17.4k
0.4
6.9
6.5k
13.8
13k
0.5
8.5
5.2k
17.3
10.5k
0.6
10.4
4.4k
21.3
8.7k
0.7
12.1
3.7k
24.2
7.5k
0.8
13.8
3.3k
27.7
6.5k
0.9
15.5
2.9k
31.1
5.8k
1.0
17.3
2.6l
34.6
5.2k
2
34.4
1.3k
70
2.6k
3
51.3
850
107
1.8k
4
68
650
144
1.3k
5
84
494
183
1.1k
6
100
402
224
900
7
115
380
269
785
8
379
284
317
698
9
143
244
370
630
10
156
211
427
527
11
168
184
490
535
12
180
161
550
500
13
190
142
635
473
14
200
125
720
450
15
210
110
816
430
16
218
98
924
413
18
233
77
1.17k
386
20
246
61
1.5k
366
TP3054-X,
TP3057-X
www.national.com
13
Typical Synchronous Application
00867406
FIGURE 4.
TP3054-X,
TP3057-X
www.national.com
14
Physical Dimensions
inches (millimeters)
unless otherwise noted
Dual-In-Line Package (M)
Order Number TP3054WM-X
NS Package Number M16B
Molded Dual-In-Line Package (N)
Order Number TP3054N-X
NS Package Number N16E
TP3054-X,
TP3057-X
www.national.com
15
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Cavity Dual-In-Line Package (V)
Order Number TP3057V-X
NS Package Number V20A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ``Banned Substances'' as defined in CSP-9-111S2.
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www.national.com
TP3054-X,
TP3057-X
Extended
T
emperature
Serial
Interface
CODEC/Filter
COMBO
Family
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