SCAN18245T
Non-Inverting Transceiver with TRI-STATE
Outputs
General Description
The SCAN18245T is a high speed, low-power bidirectional
line driver featuring separate data inputs organized into dual
9-bit bytes with byte-oriented output enable and direction
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture
with the incorporation of the defined boundary-scan test
logic and test access port consisting of Test Data Input (TDI),
Test Data Out (TDO), Test Mode Select (TMS), and Test
Clock (TCK).
Features
n
IEEE 1149.1 (JTAG) Compliant
n
Dual output enable control signals
n
TRI-STATE outputs for bus-oriented applications
n
9-bit data busses for parity applications
n
Reduced-swing outputs source 24 mA/sink 48 mA
n
Guaranteed to drive 50
transmission line to TTL input
levels of 0.8V and 2.0V
n
TTL compatible inputs
n
25 mil pitch Cerpack package
n
Includes CLAMP and HIGHZ instructions
n
Available as Known Good Die
n
Standard Microcircuit Drawing (SMD) 5962-9311501
Connection Diagram
Pin Names
Description
A1
(08)
Side A1 Inputs or TRI-STATE Outputs
Pin Names
Description
B1
(08)
Side B1 Inputs or TRI-STATE Outputs
A2
(08)
Side A2 Inputs or TRI-STATE Outputs
B2
(08)
Side B2 Inputs or TRI-STATE Outputs
G1, G2
Output Enable Pins
DIR1, DIR2
Direction of Data Flow Pins
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS100320-1
September 1998
SCAN18245T
Non-Inverting
T
ransceiver
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100320
www.national.com
Truth Tables
Inputs
A1
(08)
B1
(08)
G1
DIR1
L
L
H
H
L
L
L
L
L
H
H
H
L
H
L
L
H
X
Z
Z
Inputs
A2
(08)
B2
(08)
G2
DIR2
L
L
H
H
L
L
L
L
L
H
H
H
L
H
L
L
H
X
Z
Z
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
Functional Description
The SCAN18245 consists of two sets of nine non-inverting
bidirectional buffers with TRI-STATE outputs and is intended
for bus-oriented applications. Direction pins (DIR1 and DIR2)
LOW enables data from B ports to A ports, when HIGH en-
ables data from A ports to B ports. The Output Enable pins
(G1 and G2) when HIGH disables both A and B ports by
placing them in a high impedance condition.
Block Diagrams
A1, B1, G1 and DIR1
DS100320-2
Note: BSR stands for Boundary Scan Register.
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Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location.
Scan cell TYPE1 is intended to solely observe system data,
while TYPE2 has the additional ability to control system
data. (See IEEE Standard 1149.1
Figure 1011 for a further
description of scan cell TYPE1 and
Figure 1012 for a fur-
ther description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as well
as at each of the two internal active-high output enable sig-
nals. AOE controls the activity of the A-outputs while BOE
controls the activity of the B-outputs. Each will activate their
respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage iden-
tical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18245T device. SCAN CMOS Test Access Logic
devices do not include the IEEE 1149.1 optional identifica-
tion register. Therefore, this unique captured value can be
used as a "pseudo ID" code to confirm that the correct device
is placed in the appropriate location in the boundary scan
chain.
MSB
LSB
Instruction Code
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGHZ
All Others
BYPASS
Bypass Register Scan Chain Definition
Logic 0
DS100320-9
Instruction Register Scan Chain Definition
DS100320-10
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