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- February 1998
Highlights
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1998 National Semiconductor Corporation
PRELIMINARY
February 1998
PC87317VUL/PC97317VUL SuperI/O Plug and Play
Compatible with ACPI Compliant Controller/Extender
Highlights
General Description
The PC87317VUL/PC97317VUL are functionally identical
parts that offer a single-chip solution to the most commonly
used ISA, EISA and MicroChannel
peripherals. This fully
Plug and Play (PnP) compatible chip conforms to the
Plug
and Play ISA Specification Version 1.0a, May 5, 1994, and
meets specifications defined in the
PC97 Hardware Design
Guide. It features a Controller/Extender that is fully compli-
ant with Advanced Configuration and Power Interface (AC-
PI) Revision 1.0 requirements.
Note: All references to the PC87317VUL in this document
also refer to the PC97317VUL, unless otherwise specified.
References which are applicable to the PC97317VUL only
are italicized.
The PC87317VUL incorporates: an advanced Real-Time
Clock (RTC) device that provides both RTC timekeeping and
Advanced Power Control (APC) functionality, a Floppy Disk
Controller (FDC), a Keyboard and Mouse Controller (KBC),
two enhanced Serial Ports (UARTs) with Infrared (IR) sup-
port, a full IEEE 1284 Parallel Port, 24 General-Purpose In-
put/Output (GPIO) bit ports, three general-purpose chip
select signals that can be programmed for game port control
and a separate configuration register set for each module.
The PC87317VUL provides a LED drive output to comply
with PC97 specifications. The chip also provides support for
Power Management (PM), including a WATCHDOG
TM
timer,
and standard PC-AT address decoding for on-chip functions.
The PC87317VUL Infrared (IR) interface complies with the
HP-SIR and SHARP-IR standards, and supports all four ba-
sic protocols for Consumer Remote Control circuitry (RC-5,
RC-5 extended, RECS80 and NEC).
Outstanding Features
Among the most advanced members of National Semicon-
ductor's highly successful SuperI/O family, the PC87317VUL
offers:
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Full compatibility with ACPI Revision 1.0 requirements
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Compliancy with
PC97 Hardware Design Guide speci-
fications, including PC97 LED support
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Advanced RTC, including timekeeping and APC func-
tionality
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24 GPIO bit ports
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FDC, KBC, two enhanced UARTs, IR support, IEEE
1284 parallel port
Block Diagram
Real-Time Clock
Floppy Disk
Controller (FDC)
Keyboard + Mouse
Controller (KBC)
Management (PM)
P Address
Floppy Drive
Interface
Data Handshake
Data
X-Bus
Control
Parallel Port
(PnP)
IRQ
Control
DMA
Channels
(RTC and APC)
Plug and Play
Data and
Control
General-Purpose I/O
(GPIO) Registers
I/O Ports
Control
Control
Data and
IEEE 1284
(Logical Device 2)
(Logical Devices 0 & 1)
(Logical Device 8)
(Logical Device 4)
(Logical Device 7)
(Logical Device 3)
Ports
Serial
with IR (UART2)
Interface
Infrared
Interface
(Logical Devices 5)
Power
Serial
(UART1)
Interface
(Logical Devices 6)
Serial Port
Serial Port
TRI-STATE
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation.
IBM
, MicroChannel
, PC-AT
and PS/2
are registered trademarks of International Business Machines Corporation.
Microsoft
and Windows
are registered trademarks of Microsoft Corporation.
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Highlights
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Features
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100% compatibility with PnP requirements specified in
the "
Plug and Play ISA Specification", ISA, EISA, and
MicroChannel architectures
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A special PnP module that includes:
-- Flexible IRQs, DMAs and base addresses that meet
the PnP requirements specified by Microsoft
in
their 1995 hardware design guide for Windows
and
PnP ISA Revision 1.0A
-- PnP ISA mode (with isolation mechanism Wait for
Key state)
-- Motherboard PnP mode
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An FDC that provides:
-- A modifiable address that is referenced by a 16-bit
programmable register
-- Software compatibility with the PC8477, which con-
tains a superset of the floppy disk controller func-
tions in the
DP8473, the NEC
PD765A and the
N82077
-- 13 IRQ channel options
-- Four 8-bit DMA channel options
-- 16-byte FIFO
-- Burst and non-burst modes
-- A new, high-performance, internal, digital data sep-
arator that does not require any external filter com-
ponents
-- Support for standard 5.25" and 3.5" floppy disk
drives
-- Automatic media sense support
-- Perpendicular recording drive support
-- Three-mode Floppy Disk Drive (FDD) support
-- Full support for the IBM Tape Drive Register (TDR)
implementation of AT and PS/2 drive types
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A KBC with:
-- A modifiable address that is referenced by a 16-bit
programmable register, reported as a fixed address
in resource data
-- 13 IRQ options for the Keyboard Controller
-- 13 IRQ options for the Mouse Controller
-- An 8-bit microcontroller
-- Software compatibility with 8042AH and PC87911
microcontrollers
-- 2 KB of custom-designed program ROM
-- 256 bytes of RAM for data
-- Five programmable dedicated open drain I/O lines
for keyboard controller applications
-- Asynchronous access to two data registers and one
status register during normal operation
-- Support for both interrupt and polling
-- 93 instructions
-- An 8-bit timer/counter
-- Support for binary and BCD arithmetic
-- Operation at 8 MHz,12 MHz or 16 MHz (programma-
ble option)
-- Customizing by using the PC87323VUL, which in-
cludes a RAM-based KBC, as a development plat-
form for keyboard controller code for the
PC87317VUL
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An RTC that has:
-- A modifiable address that is referenced by a 16-bit
programmable register
-- 13 IRQ options, with programmable polarity
-- DS1287, MC146818 and PC87911 compatibility
-- 242 bytes of battery backed up CMOS RAM in two
banks
-- Selective lock mechanisms for the RTC RAM
-- Battery backed up century calendar in days, day of
the week, date of month, months, years and century,
with automatic leap-year adjustment
-- Battery backed-up time of day in seconds, minutes
and hours that allows a 12 or 24 hour format and ad-
justments for daylight savings time
-- BCD or binary format for time keeping
-- Three different maskable interrupt flags:
Periodic interrupts - At intervals from 122 msec
to 500 msec
Time-of-Month alarm - At intervals from once per
second to once per Month
Updated Ended Interrupt - Once per second
upon completion of update
-- Separate battery pin, 2.4 V operation that includes
an internal UL protection resistor
-- 2
A maximum power consumption during power
down
-- Double-buffer time registers
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ACPI Controller/Extender that supports the require-
ments of the ACPI spec (rev 1.0):
-- Power Management Timer
-- Power Button
-- Real Time Clock Alarm
-- Suspend modes via software emulation
-- PnP SCI
-- Global Lock mechanism
-- General Purpose events
-- Date of Month Alarm
-- Century byte
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An APC that controls the main power supply to the sys-
tem, using open-drain output, as follows:
Power turned on when:
-- The RTC reaches a pre-determined wake-up centu-
ry, date and time selection
-- A high to low transition occurs on the RI input signals
of the UARTs
-- A ring pulse or pulse train is detected on the RING
input signal
-- A SWITCH input signal indicates a Switch On event
with a debounce-protection
-- Any one of seven programmable Power Manage-
ment external trigger events occur
Powered turned off when:
-- A SWITCH input signal indicates a Switch Off event
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-- A Fail-safe event occurs (power-save mode detected
but the system is hung up)
-- Software turns power off
-- Any one of 10 programmable Power Management
trigger events occur
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Two Serial Ports (UART1 and 2) that provide:
-- Fully compatible with the 16550A and the 16450
-- Extended UART mode
-- 13 IRQ channel options
-- Shadow register support for write-only bit monitoring
-- UART data rates up to 1.5 Mbaud
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An enhanced UART with IR interface on the UART2 that
supports:
-- IrDA 1.0-SIR
-- ASK-IR option of SHARP-IR
-- DASK-IR option of SHARP-IR
-- Consumer Remote Control circuitry
-- DMA handshake signal routing for either 1 or 2 chan-
nels
-- A PnP compatible external transceiver
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A bidirectional parallel port that includes:
-- A modifiable address that is referenced by a 16-bit
programmable register
-- Software or hardware control
-- 13 IRQ channel options
-- Four 8-bit DMA channel options
-- Demand mode DMA support
-- An Enhanced Parallel Port (EPP) that is compatible
with the new version EPP 1.9, and is IEEE 1284
compliant
-- An Enhanced Parallel Port (EPP) that also supports
version EPP 1.7 of the Xircom specification
-- Support for an Enhanced Parallel Port (EPP) as
mode 4 of the Extended Capabilities Port (ECP)
-- An Extended Capabilities Port (ECP) that is IEEE
1284 compliant, including level 2
-- Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
-- Reduction of PCI bus utilization by supporting a de-
mand DMA mode mechanism and a DMA fairness
mechanism
-- A protection circuit that prevents damage to the par-
allel port when a printer connected to it powers up or
is operated at high voltages
-- Output buffers that can sink and source14 mA
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Three general-purpose pins for three separate program-
mable chip select signals, as follows:
-- Can be programmed for game port control
-- The Chip Select 0 (CS0) signal produces open drain
output and is powered by the V
CCH
-- The Chip Select 1 (CS1) and 2 (CS2) signals have
push-pull buffers and are powered by the main V
DD
-- Decoding of chip select signals depends on the ad-
dress and the Address Enable (AEN) signals, and
can be qualified using the Read (RD) and Write
(WR) signals.
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24 single-bit GPIO ports:
-- Modifiable addresses that are referenced by a 16-bit
programmable register
-- Programmable direction for each signal (input or out-
put)
-- Programmable drive type for each output pin (open-
drain or push-pull)
-- Programmable option for internal pull-up resistor on
each input pin
-- Configuration-Lock options
-- Several signals may be selected as interrupt triggers
-- A back-drive protection circuit
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An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus
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Clock source options:
-- Source is a 32.768 KHz crystal - an internal frequen-
cy multiplier generates all the required internal fre-
quencies.
-- Source may be either a 48 MHz or 24 MHz clock in-
put signal.
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Enhanced Power Management (PM), including:
-- Special configuration registers for power down
-- WATCHDOG timer for power-saving strategies
-- Reduced current leakage from pins
-- Low-power CMOS technology
-- Ability to shut off clocks to all modules
-- LED control powered by V
CCH
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General features include:
-- All accesses to the SuperI/O chip activate a Zero
Wait State (ZWS) signal, except for accesses to the
Enhanced Parallel Port (EPP) and to configuration
registers
-- Access to all configuration registers is through an In-
dex and a Data register, which can be relocated
within the ISA I/O address space
-- 160-pin Plastic Quad Flatpack (PQFP) package
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Table of Contents
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Table of Contents
Highlights
....................................................................................................................................................... 1
1.0
Signal/Pin Connection and Description
1.1
CONNECTION DIAGRAM ......................................................................................................... 16
1.2
SIGNAL/PIN DESCRIPTIONS ................................................................................................... 17
2.0
Configuration
2.1
HARDWARE CONFIGURATION ............................................................................................... 27
2.1.1
Wake Up Options ........................................................................................................ 27
2.1.2
The Index and Data Register Pair ............................................................................... 27
2.1.3
The Strap Pins ............................................................................................................. 28
2.2
SOFTWARE CONFIGURATION ............................................................................................... 28
2.2.1
Accessing the Configuration Registers ........................................................................ 28
2.2.2
Address Decoding ....................................................................................................... 28
2.3
THE CONFIGURATION REGISTERS ....................................................................................... 29
2.3.1
Standard Plug and Play (PnP) Register Definitions .................................................... 30
2.3.2
Configuration Register Summary ................................................................................ 33
2.4
CARD CONTROL REGISTERS ................................................................................................ 37
2.4.1
PC87317 SID Register ................................................................................................ 37
2.4.2
PC97317 SID Register ................................................................................................ 37
2.4.3
SuperI/O Configuration 1 Register (SIOC1) ................................................................ 37
2.4.4
SuperI/O Configuration 2 Register (SIOC2) ................................................................ 38
2.4.5
Programmable Chip Select Configuration Index Register ........................................... 38
2.4.6
Programmable Chip Select Configuration Data Register ............................................ 39
2.4.7
SuperI/O Configuration 3 Register (SIOC3) ................................................................ 39
2.4.8
PC97317 SRID Register .............................................................................................. 39
2.4.9
SuperI/O Configuration F Register (SIOCF), Index 2Fh .............................................. 40
2.5
KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) .................................................... 40
2.5.1
SuperI/O KBC Configuration Register ......................................................................... 40
2.6
FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) .................................................. 40
2.6.1
SuperI/O FDC Configuration Register ......................................................................... 40
2.6.2
Drive ID Register ......................................................................................................... 41
2.7
PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4) ............................... 41
2.7.1
SuperI/O Parallel Port Configuration Register ............................................................. 41
2.8
UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) .................... 42
2.8.1
SuperI/O UART2 Configuration Register ..................................................................... 42
2.9
UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 6) ................................................ 42
2.9.1
SuperI/O UART1 Configuration Register ..................................................................... 42
2.10
PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS ...................................... 42
2.10.1
CS0 Base Address MSB Register ............................................................................... 43
2.10.2
CS0 Base Address LSB Register ................................................................................ 43
2.10.3
CS0 Configuration Register ......................................................................................... 43
2.10.4
Reserved ..................................................................................................................... 43
2.10.5
CS1 Base Address MSB Register ............................................................................... 43
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