TL F 12497

PC87415

PCI-IDE

DMA

Master

Mode

Interface

Controller

PRELIMINARY

March 1996

PC87415
PCI-IDE DMA Master Mode Interface Controller

1 0 General Description

The Enhanced PCI-IDE Interface is a single-chip controller
packaged in a 100-pin PQFP It provides 2 IDE channels for
interfacing up to 4 IDE drives or 2 IDE drives and CD-ROM
directly on the PCI Local bus An enhanced DMA controller
on-chip increases system performance by providing full
scatter gather data transfers between IDE devices and sys-
tem memory without CPU intervention Four levels of both
write posting and read prefetching per channel allow the
host CPU to run concurrently with IDE cycles Programma-
ble timing functions provide maximum flexibility of timing pa-
rameters per drive for optimizing the data transfer rate per
drive Both PC compatible addressing and PCI compliant
addressing are supported by re-mapping the base address-
es A power control feature allows turning off power to the
IDE cables

The Enhanced PCI-IDE Interface connection to the PCI bus
is virtually ``glue-less'' with only one additional TTL data
buffer (optional)

This high-integration solution reduces

component count eases board design reduces cost and
increases reliability

The Enhanced PCI-IDE supports faster ATA devices using
PIO modes 1 2 3 and 4 as well as DMA modes 0 1 and 2
It comes with a full suite of software drivers for DOS 5 0
6 x Windows

3 x Windows

95 Windows NT

OS 2

2 x Novell

NetWare

3 1x 4 x and SCO UNIX

3 x

TRI-STATE

is a registered trademark of National Semiconductor Corporation

WATCHDOG

is a trademark of National Semiconductor Corporation

Novell

is a registered trademark of Novell Inc

NetWare

is a trademark of Novell Inc

Unix

is a registered trademark of AT T Bell Laboratories

Windows

and Windows

95 are registered trademarks of Microsoft Corporation

Windows NT

is a trademark of Microsoft Corporation

2 0 Features

PCI bus interface for up to 4 IDE devices

33 MHz 32-bit PCI bus data path with full parity error
reporting

16 7 MByte sec maximum IDE transfer rate

Support for 2 IDE channels (

2 IDE devices per chan-

nel)

Primary or secondary IDE addressing (1F0x 170x) in
PC compatible mode

Re-mappable base registers for full PCI compliance

Concurrent channel operation (PIO

DMA modes)

4 Double Word write FIFO per channel

4 Double Word read prefetch FIFO per channel

Enhanced DMA mode with scatter gather capability

ANSI ATA Modes 0 through 4 PIO support (internal
DMA not selected)

IORDY handshaking for PIO

ANSI ATA Modes 0 through 2 Multiword DMA support
(internal DMA selected)

Individually programmable command and recovery tim-
ing for reads and writes per channel drive for com-
mand control and data

Individually programmable data sector size for read pre-
fetches per channel

PC compatible interrupt routing of IRQ14 and IRQ15

Hardware and software chip enable disable

Optional Power Control for IDE Drives

Fully static logic design

100-pin PQFP package

TL F 12497 1

FIGURE 1 The PC87415 in a PCI Based System

C1996 National Semiconductor Corporation

RRD-B30M46 Printed in U S A

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Table of Contents

1 0 GENERAL DESCRIPTION

2 0 FEATURES

3 0 SYSTEM DIAGRAM

4 0 PIN DESCRIPTION

4 1 PCI Interface

4 2 IDE Interface

4 3 Power Control

4 4 Power and Ground

4 5 Pinout

5 0 CONFIGURATION REGISTERS

6 0 BUS MASTER IDE CONTROL AND STATUS

REGISTERS

7 0 FUNCTIONAL DESCRIPTION

7 1 PCI Interface

7 1 1 Commands

7 1 2 Termination

7 1 2 1 Target Abort in Target Mode

7 1 2 2 Retry in Target Mode

7 1 2 3 Target Abort in Master Mode

7 1 2 4 Retry in Master Mode

7 1 2 5 Disconnect in Master Mode

7 1 2 6 Master Abort in Master Mode

7 2 Data Buffers

7 2 1 Write Posting

7 2 2 Prefetch

7 2 3 Two Channel Buffer Protocol

7 3 IDE Interface

7 3 1 IDE Protocol

7 3 1 1 PIO Single Sector Reads

7 3 1 2 PIO Block Mode Reads

7 3 1 3 PIO Single Sector Writes

7 3 1 4 PIO Block Mode Writes

7 3 1 5 DMA Mode

7 3 2 Independent Timing per Drive

7 3 3 Flow Control

7 3 3 1 PIO

7 3 3 1 1 IORDY

7 3 3 1 2 Pseudo DMA

7 3 3 2 DMA

7 3 4 Interrupt Routing

7 3 5 Prefetching

7 3 6 Legacy Native Mapping Scheme

7 0 FUNCTIONAL DESCRIPTION

(Continued)

7 4 DMA Controller

7 4 1 DMA Engine

7 4 1 1 Alignment

7 4 2 DMA Engine Protocol

7 4 2 1 Scenario 1

7 4 2 1 1 Bus Master Writes

7 4 2 1 2 Bus Master Reads

7 4 2 2 Scenario 2

7 4 2 2 1 Bus Master Writes

7 4 2 2 2 Bus Master Reads

7 4 2 3 Scenario 3

7 4 2 3 1 Bus Master Writes

7 4 2 3 2 Bus Master Reads

7 4 2 4 PCI Bus Request

7 4 2 4 1 PCI Master Reads

7 4 2 4 2 PCI Master Writes

7 4 3 Master Aborts

7 4 4 Target Aborts

7 4 5 Data Synchronization

7 4 5 1 Normal

7 4 5 2 Byte Count is Less than IDE transfer

size

7 4 5 3 Byte Count is Greater than IDE transfer

size

7 4 5 4 Transfer in Progress

7 4 6 Bus Master Programming Sequence

8 0 ELECTRICAL CHARACTERISTICS

8 1 Absolute Maximum Ratings

8 2 Recommended Operating Conditions

8 3 DC Electrical Characteristics

8 4 AC Timing Specifications

8 4 1 PCI Timing Specifications

8 4 2 ATA IDE Timing Specifications

8 4 3 Configuration Register Read Cycles

8 4 4 Configuration Register Write Cycles

8 4 5 Prefetch Cycles (Read Buffer Empty)

8 4 6 Prefetch Cycles (Read Buffer Not Empty)

8 4 7 Posted Write Cycles (Medium Decode)

8 4 8 Posted Write Cycles (Fast Decode)

8 4 9 IDE Non Data Read Cycles

8 4 10 IDE Non Data Write Cycles

8 4 11 DMA Cycles

9 0 APPLICATION INFORMATION

9 1 Power Control for IDE Drives

9 2 Native Mode Interrupt Support

9 3 DMA Bus Master Control Status Register

10 0 ERRATA

10 1 Target Mode

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4 0 Pin Description

4 1 PCI INTERFACE

Name

Type

Description

AD 31 0

I O

MULTIPLEXED ADDRESS AND DATA

The direction of these pins are defined below

Phase

Target

Bus Master

Address Phase

Input

Output

Data Phase

-Read

Output

Input

-Write

Input

Output

C BE 3 0

COMMAND BYTE ENABLE

are multiplexed Bus commands and Byte enables

PAR

I O

PARITY

is even parity across AD 31 0 and C BE 3 0 PAR is an input when AD 31 0 is an input it is an

output when AD 31 0 is an output

FRAME

I 0

CYCLE FRAME

is driven by the initiator to indicate the beginning and duration of an access

TRDY

I O

TARGET READY

indicates that the current data phase of the transaction is ready to be completed

IRDY

I O

INITIATOR READY

indicates that the inltiator is ready to complete the current data phase of the transaction

STOP

indicates that the current target is requesting the initiator to stop the current transaction

DEVSEL

I O

DEVICE SELECT

when actively driven indicates the driving device has decoded its address as the target of

the current access

IDSEL

INITIALIZATION DEVICE SELECT

is used as a chip select during configuration read and write transactions

This input can be connected to one of the upper address lines AD 31 11

PERR

I O

PARITY ERROR

is used for reporting data parity errors during all PCI transactions except a Special Cycle

PERR

is an output when AD 31 0 and PAR are inputs it is an input when AD 31 0 and PAR are outputs

SERR

SYSTEM ERROR

is used for reporting address parity errors data parity errors on the Special Cycle

command or any other system error where the result will be catastrophic When reporting address parity
errors SERR

is an output

INTA

INTERRUPT

Interrupt request A

REQ

REQUEST

indicates to the bus arbiter that this device wants to use the bus and become a bus master

GNT

GRANT

indicates to this device that access to the bus has been granted

CLK

CLOCK

33 MHz PCI Clock

RST

RESET

PCI Reset

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4 0 Pin Description

(Continued)

4 2 IDE INTERFACE

Name

Type

Description

DD 15 0

I O

DRIVE DATA BUS

The 16-bit bi-directional data bus to the drive The lower 8 bits are used for non data

8-bit transfers (e g registers ECC bytes)

DA 0

I O

DRIVE ADDRESS LINE 0 OR TEST

The DA0 address line is asserted by the host to access a register or

data port in the drive It may also be used for testing during PCI Reset the rising edge of RST

samples

TEST

this pin If ``low'' all device output pins are forced to a TRI-STATE level

DA 1

I O

DRIVE ADDRESS LINE 1 OR ENABLE

During normal operation the DA1 address line is asserted by the

host to access a register or data port in the drive During PCI Reset the rising edge of RST

samples this

ENABLE

pin and places its value in the Command Register bit-0

DA 2

I O

DRIVE ADDRESS LINE 2 OR LEGACY

Dining normal operation the DA2 address line is asserted by the

host to access a register or data port in the drive During PCI Reset the rising edge of RST

samples this

LEGACY

pin and places its value in the Programming Interface Register bits 0 and 2

DIORDY

DRIVE I O CHANNEL READY

When the drive is not ready to respond to a data transfer request this

signal is negated (low) to extend the disk transfer cycle of any register access (read or write) When
DIORDY is not negated it remains in a high impedance state

DIOR

DRIVE I O READ

The read strobe signal for both channels The falling edge of DIOR

enables data from

a register or the data port of the drive onto the PCI-IDE chip

DIOW

DRIVE I O WRITE

The write strobe signal for both channels The rising edge of DIOW

clocks data from

the PCI-IDE chip into the register or the data port of the drive

DRST

DRIVE RESET

This signal from the PCI-IDE chip is asserted after power up or under software control (see

Control Register bits Table A) It is active for as long as the PCI Reset signal or if the reset bit in the
Control Register is set

CH1

CS1

CHANNEL 1 CHIP SELECT 1 AND 3

CH1

CS1

is the chip select signal to select the Command Block

Registers CH1

CS3

is the chip select signal to select the Control Block Registers

CH1

CS3

CH2

CS1

CHANNEL 2 CHIP SELECT 1 AND 3

CH2

CS1

is the chip select signal to select the Command Block

Registers CH2

CS3

is the chip select signal to select the Control Block Registers

CH2

CS3

CH1

INTRQ

DRIVE INTERRUPTS

These signals are used to interrupt the host system CH1

INTRQ is asserted only

when the drive(s) on channel 1 has a pending interrupt and the host has cleared nIEN in the drive's

CH2

INTRQ

Device Control Register CH2

INTRQ is asserted only when the drive(s) on channel 2 has a pending

interrupt and the host has cleared nIEN in the Device Control Register

CH1

CHANNEL 1 DMA REQUEST

This signal is used when using the internal DMA controller When this

signal is asserted the selected drive on channel 1 is ready to transfer data

DMARQ

CH2

CHANNEL 2 DMA REQUEST

This signal is used when using the internal DMA controller When this

signal is asserted the selected drive on channel 2 is ready to transfer data

DMARQ

CH1

CHANNEL 1 DMA ACKNOWLEDGE

This signal is used when using the internal DMA controller When

asserted it signals the selected drive on channel 1 that data has been accepted or that data is available

DMACK

CH2

CHANNEL 2 DMA ACKNOWLEDGE

This signal is used when using the internal DMA controller When

asserted it signals the selected drive on channel 2 that data has been accepted or that data is available

DMACK

IRQ14

mirrors CH1

INT if Legacy mode is enabled

IRQ15

mirrors CH2

INT if Legacy mode is enabled

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