TL F 11362

PC87311APC87312

(SuperIO

IIIII)

Floppy

Disk

Controller

with

Dual

UARTs

Parallel

Port

and

IDE

Interface

October 1993

PC87311A PC87312 (SuperI O

II III)

Floppy Disk Controller with Dual UARTs
Parallel Port and IDE Interface

General Description

The PC87311A 12 incorporates a floppy disk controller
(FDC) two full function UARTs a bidirectional parallel port
and IDE interface control logic in one chip The PC87311A
includes standard AT XT address decoding for on-chip
functions and a Configuration Register offering a single
chip solution to the most commonly used IBM

PC-XT

and PC-AT

peripherals The PC87312 includes

standard AT address decoding for on-chip functions and a
Configuration Register set offering a single chip solution to
the most commonly used ISA EISA and Micro Channel pe-
ripherals

The on-chip FDC is software compatible to the PC8477
which contains a superset of the DP8473 and NEC mPD765
and the N82077 floppy disk controller functions The on-
chip analog data separator requires no external compo-
nents and supports the 4 Mb drive format as well as the
other standard floppy drives used with 5 25

and 3 5

me-

dia

In the PC87311A

the UARTs are equivalent to two

INS8250N-Bs or NS16450s The bidirectional parallel port
maintains complete compatibility with the IBM PC XT and
AT In the PC87312 the UARTs are equivalent to two
NS16450s or PC16550s The bidirectional parallel port
maintains complete compatibility with the ISA EISA and Mi-
cro Channel parallel ports

The IDE control logic provides a complete IDE interface ex-
cept for the signal buffers The Configuration Registers con-
sist of three byte-wide registers An Index and a Data Regis-
ter which can be relocated within the ISA I O address space
access the Configuration Registers

Features

100% compatible with IBM PC XT and AT architec-
tures (PC87311A) or ISA EISA and Micro Channel ar-
chitectures (PC87312)

FDC

Software compatible with the DP8473 the 765A and
the N82077
16-byte FIFO (default disabled)
Burst and Non-Burst modes
Perpendicular Recording drive support
High performance internal analog data separator (no
external filter components required)
Low power CMOS with power down mode

UARTs

Software compatible with the INS8250N-B and the
NS16450 (PC87311A) or PC16550A and PC16450
(PC87312)

Parallel Port

Bidirectional under either software or hardware
control
Compatible with all IBM PC XT and AT architectures
(PC87311A) or all ISA EISA and Micro Channel ar-
chitectures (PC87312)
Back Voltage protection circuit against damage
caused when printer is powered up

IDE Control Logic

Provides a complete IDE interface except for option-
al buffers

Address Decoder

Provides selection of all primary and secondary ISA
addresses including COM 1 � 4

100-pin PQFP package

The PC87311A and PC87312 are pin compatible

Block Diagram

TL F 11362 � 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation

SuperI O

is a trademark of National Semiconductor Corporation

IBM

PC-AT

PC-XT

and PS 2

are registered trademarks of International Business Machines Corporation

C1995 National Semiconductor Corporation

RRD-B30M75 Printed in U S A

Table of Contents

1 0 PIN DESCRIPTION

2 0 CONFIGURATION REGISTERS

2 1 Overview

2 2 Software Configuration

2 3 Hardware Configuration

2 4 Index and Data Registers

2 5 Base Configuration Registers

2 5 1 Function Enable Register (FER)

2 5 2 Function Address Register (FAR)

2 5 3 Power and Test Register (PTR)

2 6 Power Down Options

2 7 Power Up Procedure and Considerations

2 7 1 Crystal Stabilization

2 7 2 UART Power-Up

2 7 3 FDC Power-Up

3 0 FDC REGISTER DESCRIPTION

3 1 Status Register A (SRA)

3 1 1 SRA

PS 2 Mode

3 1 2 SRA

Model 30 Mode

3 2 Status Register B (SRB)

3 2 1 SRB

PS 2 Mode

3 2 2 SRB

Model 30 Mode

3 3 Digital Output Register (DOR)

3 4 Tape Drive Register (TDR)

3 5 Main Status Register (MSR)

3 6 Data Rate Select Register (DSR)

3 7 Data Register (FIFO)

3 8 Digital Input Register (DIR)

3 8 1 DIR

PC-AT Mode

3 8 2 DIR

PS 2 Mode

3 8 3 DIR

Model 30 Mode

3 9 Configuration Control Register (CCR)

3 9 1 CCR

PC-AT and PS 2 Modes

3 9 2 CCR

Model 30 Mode

3 10 Result Phase Status Registers

3 10 1 Status Register 0 (ST0)

3 10 2 Status Register 1 (ST1)

3 10 3 Status Register 2 (ST2)

3 10 4 Status Register 3 (ST3)

4 0 FDC COMMAND SET DESCRIPTION

4 1 Command Set Summary

4 2 Command Description

4 2 1 Configure Command

4 2 2 Dumpreg Command

4 2 3 Format Track Command

4 2 4 Invalid Command

4 2 5 Lock Command

4 2 6 Mode Command

4 2 7 NSC Command

4 2 8 Perpendicular Mode Command

4 2 9 Read Data Command

4 2 10 Read Deleted Data Command

4 2 11 Read ID Command

4 2 12 Read A Track Command

4 2 13 Recalibrate Command

4 2 14 Relative Seek Command

4 2 15 Scan Commands

4 2 16 Seek Command

4 2 17 Sense Drive Status Command

4 2 18 Sense Interrupt Command

4 2 19 Set Track Command

4 2 20 Specify Command

4 2 21 Verify Command

4 2 22 Version Command

4 2 23 Write Data Command

4 2 24 Write Deleted Data Command

5 0 FDC FUNCTIONAL DESCRIPTION

5 1 Microprocessor Interface

5 2 Modes of Operation

5 3 Controller Phases

5 3 1 Command Phase

5 3 2 Execution Phase

5 3 2 1 DMA Mode

FIFO Disabled

5 3 2 2 DMA Mode

FIFO Enabled

5 3 2 3 Interrupt Mode

FIFO Disabled

5 3 2 4 Interrupt Mode

FIFO Enabled

5 3 2 5 Software Polling

5 3 3 Result Phase

5 3 4 Idle Phase

5 3 5 Drive Polling Phase

5 4 Data Separator

5 5 Crystal Oscillator

5 6 Perpendicular Recording Mode

5 7 Data Rate Selection

5 8 Write Precompensation

5 9 FDC Low Power Mode Logic

5 10 Reset Operation

6 0 SERIAL PORTS

6 1 Introduction

6 2 PC87311A Serial Ports

6 2 1 Serial Port Registers

6 2 2 Line Control Register (LCR)

6 2 3 Programmable Baud Rate Generator

6 2 4 Line Status Register (LSR)

6 2 5 Interrupt Identification Register (IIR)

6 2 6 Interrupt Enable Register (IER)

6 2 7 MODEM Control Register (MCR)

6 2 8 MODEM Status Register (MSR)

6 2 9 Scratchpad Register (SCR)

6 3 PC87312 Serial Ports

6 3 1 Serial Port Registers

6 3 2 Line Control Register (LCR)

6 3 3 Programmable Baud Rate Generator

Table of Contents

6 3 4 Line Status Register (LSR)

6 3 5 FIFO Control Register (FCR)

6 3 6 Interrupt Identification Register (IIR)

6 3 7 Interrupt Enable Register (IER)

6 3 8 MODEM Control Register (MCR)

6 3 9 MODEM Status Register (MSR)

6 3 10 Scratchpad Register (SCR)

7 0 PARALLEL PORT

7 1 Introduction

7 2 Data Register (DTR)

7 3 Status Register (STR)

7 4 Control Register (CTR)

8 0 INTEGRATED DEVICE ELECTRONICS

INTERFACE (IDE)

8 1 Introduction

8 2 IDE Signals

9 0 DEVICE DESCRIPTION

9 1 DC Electrical Characteristics

9 2 AC Electrical Characteristics

9 2 1 AC Test Conditions

9 2 2 Clock Timing

9 2 3 Microprocessor Interface Timing

9 2 4 Baudout Timing

9 2 5 Transmitter Timing

9 2 6 Receiver Timing

9 2 7 MODEM Control Timing

9 2 8 DMA Timing

9 2 9 Reset Timing

9 2 10 Write Data Timing

9 2 11 Drive Control Timing

9 2 12 Read Data Timing

9 2 13 IDE Timing

9 2 14 Parallel Port Timing

10 0 REFERENCE SECTION

10 1 Mnemonic Definitions for FDC Commands

10 2 Example Four Drive Circuit

Using the PC87311A 12

List of Figures

FIGURE 2-1

PC87311A 87312 Configuration Registers

FIGURE 3-1

FDC Functional Block Diagram

FIGURE 4-1

IBM Perpendicular and ISO Formats Supported by Format Command

FIGURE 5-1

FDC Data Separator Block Diagram

FIGURE 5-2

PC87311A 87312 Dynamic Window Margin Performance

FIGURE 5-3

Read Data Algorithm

State Diagram

FIGURE 5-4

Perpendicular Recording Drive R W Head and Pre-Erase Head

FIGURE 6-1

PC87311A Composite Serial Data

FIGURE 6-2

PC87312 Composite Serial Data

FIGURE 9-1

Clock Timing

FIGURE 9-2

Microprocessor Read Timing

FIGURE 9-3

Microprocessor Write Timing

FIGURE 9-4

Baudout Timing

FIGURE 9-5

Transmitter Timing

FIGURE 9-6a

Receiver Timing

FIGURE 9-6b

PC87312 FIFO Mode Receiver Timing

FIGURE 9-6c

PC87312 Timeout Receiver Timing

FIGURE 9-7

MODEM Control Timing

FIGURE 9-8

DMA Timing

FIGURE 9-9

Reset Timing

FIGURE 9-10

Write Data Timing

FIGURE 9-11

Drive Control Timing

FIGURE 9-12

Read Data Timing

FIGURE 9-13

IDE Timing

FIGURE 9-14

Parallel Port Interrupt Timing (Compatible Mode)

FIGURE 9-15

Parallel Port Interrupt Timing (Extended Mode)

FIGURE 9-16

Typical Parallel Port Data Exchange

FIGURE 10-1

PC87311A 87312 Four Floppy Drive Circuit

FIGURE 10-2

IDE Interface Signal Equations

FIGURE 10-3

PC87311A 87312 Adapter Card Schematic

List of Tables

TABLE 2-1

Default Configurations Controlled by Hardware

TABLE 2-2

Index and Data Register Optional Locations

TABLE 2-3

Primary and Secondary Drive Address Selection

TABLE 2-4

Encoded Drive and Motor Pin Information

TABLE 2-5

Parallel Port Addresses

TABLE 2-6a

COM Port Selection for UART1

TABLE 2-6b

COM Port Selection for UART2

TABLE 2-7

Address Selection for COM3 and COM4

TABLE 3-1

TABLE 3-2

Drive Enable Values

TABLE 3-3

Tape Drive Assignment Values

TABLE 3-4

Write Precompensation Delays

TABLE 3-5

Default Precompensation Delays

TABLE 3-6

Data Rate Select Encoding

TABLE 4-1

Typical Format Gap Length Values

TABLE 4-2

DENSEL Encoding

TABLE 4-3

DENSEL Default Encoding

TABLE 4-4

Effect of Drive Mode and Data Rate on Format and Write Commands

TABLE 4-4a

Effect of GAP and WG on Format and Write Commands

TABLE 4-5

Sector Size Selection

TABLE 4-6

SK Effect on Read Data Command

TABLE 4-7

Result Phase Termination Values with No Error

TABLE 4-8

SK Effect on Read Deleted Data Command

TABLE 4-9

Maximum Recalibrate Step Pulses Based on R255 and ETR

TABLE 4-10

Scan Command Termination Values

TABLE 4-11

Status Register 0 Termination Codes

TABLE 4-12

Set Track Register Address

TABLE 4-13

Step Rate (SRT) Values

TABLE 4-14

Motor Off Time (MFT) Values

TABLE 4-15

Motor On Time (MNT) Values

TABLE 4-16

Verify Command Result Phase Table

TABLE 6-1

PC87311A UART Register Addresses (AEN

TABLE 6-2

PC87311A Register Summary for an Individual UART Channel

TABLE 6-3

PC87311A UART Reset Configuration

TABLE 6-4

PC87311A UART Divisors Baud Rates and Clock Frequencies

TABLE 6-5

PC87311A Interrupt Control Functions

TABLE 6-6

PC87312 UART Register Addresses (AEN

TABLE 6-7

PC87312 Register Summary for an Individual UART Channel

TABLE 6-8

PC87312 UART Reset Configuration

TABLE 6-9

PC87312 UART Divisors Baud Rates and Clock Frequencies

TABLE 6-10

PC87312 Interrupt Control Functions

TABLE 7-1

Parallel Interface Register Addresses

TABLE 7-2

Data Register Read and Write Modes

TABLE 7-3

Parallel Port Mode of Operation

TABLE 7-4

Parallel Port Reset States

TABLE 8-1

IDE Registers and Their ISA Addresses

TABLE 9-1

Nominal t

ICP

DRP

Values

TABLE 9-2

Minimum t

WDW

Values

TABLE 10-1

PC87311A 87312 Four Floppy Drive Encoding

Электронный компонент: PC87311A